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2019-01-29xlnx-zynqmp: Don't create rpu-cluster if there are no RPUsPeter Maydell
If we aren't going to create any RPUs, then don't create the rpu-cluster unit. This allows us to add an assertion to the cluster object that it contains at least one CPU, which helps to avoid bugs in creating clusters and putting CPUs in them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190121184314.14311-1-peter.maydell@linaro.org
2019-01-29checkpatch: Don't emit spurious warnings about block commentsPeter Maydell
In checkpatch we attempt to check for and warn about block comments which start with /* or /** followed by a non-blank. Unfortunately a bug in the regex meant that we would incorrectly warn about comments starting with "/**" with no following text: git show 9813dc6ac3954d58ba16b3920556f106f97e1c67|./scripts/checkpatch.pl - WARNING: Block comments use a leading /* on a separate line #34: FILE: tests/libqtest.h:233: +/** The sequence "/\*\*?" was intended to match either "/*" or "/**", but Perl's semantics for '?' allow it to backtrack and try the "matches 0 chars" option if the "matches 1 char" choice leads to a failure of the rest of the regex to match. Switch to "/\*\*?+" which uses what perlre(1) calls the "possessive" quantifier form: this means that if it matches the "/**" string it will not later backtrack to matching just the "/*" prefix. The other end of the regex is also wrong: it is attempting to check for "/* or /** followed by something that isn't just whitespace", but [ \t]*.+[ \t]* will match on pure whitespace. This is less significant but means that a line with just a comment-starter followed by trailing whitespace will generate an incorrect warning about block comment style as well as the correct error about trailing whitespace which a different checkpatch test emits. Fixes: 8c06fbdf36bf4d ("scripts/checkpatch.pl: Enforce multiline comment syntax") Reported-by: Thomas Huth <thuth@redhat.com> Reported-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20190118165050.22270-1-peter.maydell@linaro.org
2019-01-29tests/microbit-test: Check nRF51 UART functionalityJulia Suvorova
Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20190123120759.7162-4-jusual@mail.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29tests/microbit-test: Make test independent of global_qtestJulia Suvorova
Using of global_qtest is not required here. Let's replace functions like readl() with the corresponding qtest_* counterparts. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190123120759.7162-3-jusual@mail.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29tests/libqtest: Introduce qtest_init_with_serial()Julia Suvorova
Run qtest with a socket that connects QEMU chardev and test code. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190123120759.7162-2-jusual@mail.ru Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29memory: add memory_region_flush_rom_device()Stefan Hajnoczi
ROM devices go via MemoryRegionOps->write() callbacks for write operations and do not dirty/invalidate that memory. Device emulation must be able to mark memory ranges that have been modified internally (e.g. using memory_region_get_ram_ptr()). Introduce the memory_region_flush_rom_device() API for this purpose. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190123212234.32068-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix block comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: Don't clear supported PMU events when initializing PMCEID1Aaron Lindsay OS
A bug was introduced during a respin of: commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190123195814.29253-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29MAINTAINERS: update microbit ARM board filesStefan Hajnoczi
New source files were added without corresponding ./MAINTAINERS file entries. Let's get things up to date. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190123183352.11025-1-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs writePeter Maydell
In cpu_signal_handler() for aarch64 hosts, currently we parse the faulting instruction to see if it is a load or a store. Since the 3.16 kernel (~2014), the kernel has provided us with the syndrome register for a fault, which includes the WnR bit. Use this instead if it is present, only falling back to instruction parsing if not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108180014.32386-1-peter.maydell@linaro.org
2019-01-29exec.c: Use correct attrs in cpu_memory_rw_debug()Peter Maydell
In the softmmu version of cpu_memory_rw_debug(), we ask the CPU for the attributes to use for the virtual memory access, and we correctly use those to identify the address space index. However, we were not passing them in to the address_space_write_rom() and address_space_rw() functions. The effect of this was that a memory access from the gdbstub to a device which had behaviour that was sensitive to the memory attributes (such as some ARMv8M NVIC registers) was incorrectly always performed as if non-secure, rather than using the right security state for the CPU's current state. Fixes: https://bugs.launchpad.net/qemu/+bug/1812091 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190117133834.7480-1-peter.maydell@linaro.org
2019-01-29tests/microbit-test: add TWI stub device testStefan Hajnoczi
This test verifies that we read back the expected I2C WHO_AM_I register values for the accelerometer/magnetometer. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-3-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29arm: Stub out NRF51 TWI magnetometer/accelerometer detectionSteffen Görtz
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0Luc Michel
a TID or PID value means "any thread" (resp. "any process"). This commit fixes the different combinations when at least one value is 0. When both are 0, the function now returns the first attached CPU, instead of the CPU with TID 1, which is not necessarily attached or even existent. When PID is specified but TID is 0, the function returns the first CPU in the process, or NULL if the process does not exist or is not attached. In other cases, it returns the corresponding CPU, while ignoring the PID check when PID is 0. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190119140000.11767-1-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: v8m: Ensure IDAU is respected if SAU is disabledThomas Roth
The current behavior of v8m_security_lookup in helper.c only checks whether the IDAU specifies a higher security if the SAU is enabled. If SAU.ALLNS is set to 1, this will lead to addresses being treated as non-secure, even though the IDAU indicates that they must be secure. This patch changes the behavior to also check the IDAU if the SAU is currently disabled. (This brings the behaviour here into line with the v8M Arm ARM SecurityCheck() pseudocode.) Signed-off-by: Thomas Roth <code@stacksmashing.net> Message-id: CAGGekkuc+-tvp5RJP7CM+Jy_hJF7eiRHZ96132sb=hPPCappKg@mail.gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added pseudocode ref to the commit message, fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: Fix validation of 32-bit address spaces for aa32Richard Henderson
When tsz == 0, aarch32 selects the address space via exclusion, and there are no "top_bits" remaining that require validation. Fixes: ba97be9f4a4 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190125184913.5970-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-28Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into stagingPeter Maydell
Backend vector enhancements Dynamic tlb resizing # gpg: Signature made Mon 28 Jan 2019 15:57:19 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190128: (23 commits) cputlb: Remove static tlb sizing tcg/tci: enable dynamic TLB sizing tcg/mips: enable dynamic TLB sizing tcg/mips: Fix tcg_out_qemu_ld_slow_path tcg/arm: enable dynamic TLB sizing tcg/riscv: enable dynamic TLB sizing tcg/s390: enable dynamic TLB sizing tcg/sparc: enable dynamic TLB sizing tcg/ppc: enable dynamic TLB sizing tcg/aarch64: enable dynamic TLB sizing tcg/i386: enable dynamic TLB sizing tcg: introduce dynamic TLB sizing cputlb: do not evict empty entries to the vtlb tcg/aarch64: Implement vector minmax arithmetic tcg/aarch64: Implement vector saturating arithmetic tcg/i386: Implement vector minmax arithmetic tcg/i386: Implement vector saturating arithmetic tcg/i386: Split subroutines out of tcg_expand_vec_op tcg: Add opcodes for vector minmax arithmetic tcg: Add opcodes for vector saturated arithmetic ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-28cputlb: Remove static tlb sizingRichard Henderson
Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB, remove the define and the old code. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/tci: enable dynamic TLB sizingRichard Henderson
This is automatic due to TCI using the other softtlb macros. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/mips: enable dynamic TLB sizingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/mips: Fix tcg_out_qemu_ld_slow_pathRichard Henderson
Patch the branch after it has been emitted rather than before it exists. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/arm: enable dynamic TLB sizingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/s390: enable dynamic TLB sizingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/sparc: enable dynamic TLB sizingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/ppc: enable dynamic TLB sizingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/aarch64: enable dynamic TLB sizingRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/i386: enable dynamic TLB sizingEmilio G. Cota
As the following experiments show, this series is a net perf gain, particularly for memory-heavy workloads. Experiments are run on an Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz. 1. System boot + shudown, debian aarch64: - Before (v3.1.0): Performance counter stats for './die.sh v3.1.0' (10 runs): 9019.797015 task-clock (msec) # 0.993 CPUs utilized ( +- 0.23% ) 29,910,312,379 cycles # 3.316 GHz ( +- 0.14% ) 54,699,252,014 instructions # 1.83 insn per cycle ( +- 0.08% ) 10,061,951,686 branches # 1115.541 M/sec ( +- 0.08% ) 172,966,530 branch-misses # 1.72% of all branches ( +- 0.07% ) 9.084039051 seconds time elapsed ( +- 0.23% ) - After: Performance counter stats for './die.sh tlb-dyn-v5' (10 runs): 8624.084842 task-clock (msec) # 0.993 CPUs utilized ( +- 0.23% ) 28,556,123,404 cycles # 3.311 GHz ( +- 0.13% ) 51,755,089,512 instructions # 1.81 insn per cycle ( +- 0.05% ) 9,526,513,946 branches # 1104.641 M/sec ( +- 0.05% ) 166,578,509 branch-misses # 1.75% of all branches ( +- 0.19% ) 8.680540350 seconds time elapsed ( +- 0.24% ) That is, a 4.4% perf increase. 2. System boot + shutdown, ubuntu 18.04 x86_64: - Before (v3.1.0): 56100.574751 task-clock (msec) # 1.016 CPUs utilized ( +- 4.81% ) 200,745,466,128 cycles # 3.578 GHz ( +- 5.24% ) 431,949,100,608 instructions # 2.15 insn per cycle ( +- 5.65% ) 77,502,383,330 branches # 1381.490 M/sec ( +- 6.18% ) 844,681,191 branch-misses # 1.09% of all branches ( +- 3.82% ) 55.221556378 seconds time elapsed ( +- 5.01% ) - After: 56603.419540 task-clock (msec) # 1.019 CPUs utilized ( +- 10.19% ) 202,217,930,479 cycles # 3.573 GHz ( +- 10.69% ) 439,336,291,626 instructions # 2.17 insn per cycle ( +- 14.14% ) 80,538,357,447 branches # 1422.853 M/sec ( +- 16.09% ) 776,321,622 branch-misses # 0.96% of all branches ( +- 3.77% ) 55.549661409 seconds time elapsed ( +- 10.44% ) No improvement (within noise range). Note that for this workload, increasing the time window too much can lead to perf degradation, since it flushes the TLB *very* frequently. 3. x86_64 SPEC06int: x86_64-softmmu speedup vs. v3.1.0 for SPEC06int (test set) Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake) 5.5 +------------------------------------------------------------------------+ | +-+ | 5 |-+.................+-+...............................tlb-dyn-v5.......+-| | * * | 4.5 |-+.................*.*................................................+-| | * * | 4 |-+.................*.*................................................+-| | * * | 3.5 |-+.................*.*................................................+-| | * * | 3 |-+......+-+*.......*.*................................................+-| | * * * * | 2.5 |-+......*..*.......*.*.................................+-+*...........+-| | * * * * * * | 2 |-+......*..*.......*.*.................................*..*...........+-| | * * * * * * +-+ | 1.5 |-+......*..*.......*.*.................................*..*.*+-+.*+-+.+-| | * * *+-+ * * +-+ *+-+ +-+ +-+ * * * * * * | 1 |++++-+*+*++*+*++*++*+*++*+*+++-+*+*+-++*+-++++-++++-+++*++*+*++*+*++*+++| | * * * * * * * * * * * * * * * * * * * * * * * * * * | 0.5 +------------------------------------------------------------------------+ 400.perlb401.bzip403.g429445.g456.hm462.libq464.h471.omn47483.xalancbgeomean png: https://imgur.com/YRF90f7 That is, a 1.51x average speedup over the baseline, with a max speedup of 5.17x. Here's a different look at the SPEC06int results, using KVM as the baseline: x86_64-softmmu slowdown vs. KVM for SPEC06int (test set) Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake) 25 +---------------------------------------------------------------------------+ | +-+ +-+ | | * * +-+ v3.1.0 | | * * +-+ tlb-dyn-v5 | | * * * * +-+ | 20 |-+.................*.*.............................*.+-+......*.*........+-| | * * * # # * * | | +-+ * * * # # * * | | * * * * * # # * * | 15 |-+......*.*........*.*.............................*.#.#......*.+-+......+-| | * * * * * # # * #|# | | * * * * +-+ * # # * +-+ | | * * +-+ * * ++-+ +-+ * # # * # # +-+ | | * * +-+ * * * ## *| +-+ * # # * # # +-+ | 10 |-+......*.*..*.+-+.*.*........*.##.......++-+.*.+-+*.#.#......*.#.#.*.*..+-| | * * * +-+ * * * ## +-+ *# # * # #* # # +-+ * # # * * | | * * * # # * * +-+ * ## * +-+ *# # * # #* # # * * * # # *+-+ | | * * * # # * * * +-+ * ## * # # *# # * # #* # # * * * # # * ## | 5 |-+......*.+-+*.#.#.*.*..*.#.#.*.##.*.#.#.*#.#.*.#.#*.#.#.*.*..*.#.#.*.##.+-| | * # #* # # * +-+* # # * ## * # # *# # * # #* # # * * * # # * ## | | * # #* # # * # #* # # * ## * # # *# # * # #* # # * +-+* # # * ## | | ++-+ * # #* # # * # #* # # * ## * # # *# # * # #* # # * # #* # # * ## | |+++*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+*+#+#+*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+++| 0 +---------------------------------------------------------------------------+ 400.perlbe401.bzi403.gc429445.go456.h462.libqu464.h471.omne4483.xalancbmgeomean png: https://imgur.com/YzAMNEV After this series, we bring down the average SPEC06int slowdown vs KVM from 11.47x to 7.58x. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20190116170114.26802-4-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota
Disabled in all TCG backends for now. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20190116170114.26802-3-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28cputlb: do not evict empty entries to the vtlbEmilio G. Cota
Currently we evict an entry to the victim TLB when it doesn't match the current address. But it could be that there's no match because the current entry is empty (i.e. all -1's, for instance via tlb_flush). Do not evict the entry to the vtlb in that case. This change will help us keep track of the TLB's use rate, which we'll use to implement a policy for dynamic TLB sizing. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20190116170114.26802-2-cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/aarch64: Implement vector minmax arithmeticRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/aarch64: Implement vector saturating arithmeticRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/i386: Implement vector minmax arithmeticRichard Henderson
The avx instruction set does not directly provide MO_64. We can still implement 64-bit with comparison and vpblendvb. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/i386: Implement vector saturating arithmeticRichard Henderson
Only MO_8 and MO_16 are implemented, since that's all the instruction set provides. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg/i386: Split subroutines out of tcg_expand_vec_opRichard Henderson
This routine was becoming too large. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: Add opcodes for vector minmax arithmeticRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: Add opcodes for vector saturated arithmeticRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: Add write_aofs to GVecGen4Richard Henderson
This allows writing 2 output, 3 input operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: Add gvec expanders for nand, nor, eqvRichard Henderson
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28tcg: Add logical simplifications during gvec expandRichard Henderson
We handle many of these during integer expansion, and the rest of them during integer optimization. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-28Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into stagingPeter Maydell
Pull request # gpg: Signature made Fri 25 Jan 2019 22:06:08 GMT # gpg: using RSA key 7DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: ide/via: Implement and use native PCI IDE mode ide/via: Rename functions to match device name ide/via: Remove vt82c686b_init_ports() function sii3112: Remove duplicated code and use PCI IDE ops instead ide: Get rid of CMD646BAR struct cmd646: Move PCI IDE specific functions to ide/pci.c cmd646: Remove IDEBus from CMD646BAR cmd646: Remove unused variable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-25ide/via: Implement and use native PCI IDE modeBALATON Zoltan
This device only implemented ISA compatibility mode and native PCI IDE mode was missing but no clients actually need ISA mode but to the contrary, they usually want to switch to and use device in native PCI IDE mode. Therefore implement native PCI mode and switch default to that. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-id: c323f08c59b9931310c5d92503d370f77ce3a557.1548160772.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25ide/via: Rename functions to match device nameBALATON Zoltan
The device is called via-ide and the modelled IDE controller is not specific to 82C686B but is also usable independently. Therefore, change function name prefixes accordingly to match device name. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-id: 2905ced862c8d2ad509d73152171ce2472d72605.1548160772.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25ide/via: Remove vt82c686b_init_ports() functionBALATON Zoltan
This function is only called once from vt82c686b_ide_realize() and its content is simple enough to not need a separate function but be included in realize directly (as done in other IDE models except PIIX currently). Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-id: 47d854e0fa41dad6861107eac61327c247965566.1548160772.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25sii3112: Remove duplicated code and use PCI IDE ops insteadBALATON Zoltan
Parts of the SiI3112 mmio are identical to PCI IDE registers so we can use the corresponding functions that were factored out into ide/pci.c. This removes code duplication and simplifies the SiI3112 model which also helped to spot a copy paste error where reading status of the 2nd channel read the 1st channel instead. This is also fixed here. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 793b6a7934ef2bba26b8d066bec446019efa6c5d.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25ide: Get rid of CMD646BAR structBALATON Zoltan
Now that no CMD646 specific parts are left in CMD646BAR (all remaining members are really PCI IDE specific) this struct can be deleted moving the memory regions for PCI IDE BARs to PCIIDEState where they better belong. The CMD646 PCI IDE model is adjusted accordingly. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 4b6cb2ae150dc0d21178209e4beb1e35140a7325.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Move PCI IDE specific functions to ide/pci.cBALATON Zoltan
The io mem ops callbacks are not specific to CMD646 but really follow the PCI IDE spec so move these from cmd646.c to pci.c to allow other PCI IDE implementations to use them. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: a2b1b2b74afdc78330b8b75605687f683a249635.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Remove IDEBus from CMD646BARBALATON Zoltan
The cmd646 io mem ops callbacks only need the IDEBus which is currently passed via a CMD646BAR struct. No need to wrap it up like that, we can pass it directly to these callbacks which then allows to drop the IDEBus from the CMD646BAR. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 7a31c155c9899869794499d841d30c7ef32aae47.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25cmd646: Remove unused variableBALATON Zoltan
There was a pointer to PCIIDEState in CMD646BAR which was set but not used afterwards. Get rid of this unused variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1e352f091aa601fb2e19771aac46529fe278dd91.1547166960.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
2019-01-25Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/python-next-pull-request' into staging Python 3 compatibility fixes # gpg: Signature made Fri 25 Jan 2019 14:04:56 GMT # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/python-next-pull-request: decodetree: re.fullmatch was added in 3.4 device-crash-test: Python 3 compatibility fix Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-25Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging MIPS queue for January 25, 2019 # gpg: Signature made Fri 25 Jan 2019 13:25:57 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-25-2019: docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models qemu-doc: Add nanoMIPS ISA information tests: tcg: mips: Remove old directories tests: tcg: mips: Add two new Makefiles tests: tcg: mips: Move source files to new locations MAINTAINERS: Update MIPS sections target/mips: Add I6500 core configuration target/mips: nanoMIPS: Fix branch handling disas: nanoMIPS: Amend DSP instructions related comments target/mips: Extend gen_scwp() functionality to support EVA target/mips: Correct the second argument type of cpu_supports_isa() target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers target/mips: nanoMIPS: Remove an unused macro target/mips: nanoMIPS: Remove duplicate macro definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-10 21:20:05 +0000