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2019-05-28Merge remote-tracking branch ↵Peter Maydell
'remotes/amarkovic/tags/mips-queue-may-19-2019-v3' into staging MIPS queue for May 19th, 2019 - v3 # gpg: Signature made Sun 26 May 2019 17:07:07 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-may-19-2019-v3: BootLinuxSshTest: Test some userspace commands on Malta target/mips: realign comments to fix checkpatch warnings target/mips: add or remove space to fix checkpatch errors linux-user: fix __NR_semtimedop undeclared error mips: Decide to map PAGE_EXEC in map_address target/mips: Refactor and fix INSERT.<B|H|W|D> instructions target/mips: Refactor and fix COPY_U.<B|H|W> instructions target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-28Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' ↵Peter Maydell
into staging RISC-V Patches for the 4.1 Soft Freeze, Part 1 This tag contains a handful of patches that I'd like to target for 4.1: * An emulation for SiFive's GPIO device. * A fix to disallow sfence.vma from userspace. * Additional decodetree cleanups that should have no functional impact. * C extension emulation fidelity fixes that were noticed as part of that cleanup process. * A new "spike" target, along with the deprecation of a handful of old targets and CPUs. * Some initial infastructure related to the hypervisor extension. * An emulation fidelity fix that prevents prevents arbitrary bits in the SIP CSR from being set. * A small performance improvement that avoids excessive TLB flushing when the ASID does not change. This time I've used a new testing workflow: I've tested on both 32-bit and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot flow. # gpg: Signature made Sat 25 May 2019 01:05:57 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.1-sf0: (29 commits) target/riscv: Only flush TLB if SATP.ASID changes target/riscv: More accurate handling of `sip` CSR target/riscv: Add checks for several RVC reserved operands target/riscv: Add the HGATP register masks target/riscv: Add the HSTATUS register masks target/riscv: Add Hypervisor CSR macros target/riscv: Allow setting mstatus virtulisation bits target/riscv: Add the MPV and MTL mstatus bits target/riscv: Improve the scause logic target/riscv: Trigger interrupt on MIP update asynchronously target/riscv: Mark privilege level 2 as reserved riscv: spike: Add a generic spike machine target/riscv: Deprecate the generic no MMU CPUs target/riscv: Add a base 32 and 64 bit CPU target/riscv: Create settable CPU properties riscv: virt: Allow specifying a CPU via commandline linux-user/riscv: Add the CPU type as a comment target/riscv: Remove unused include of riscv_htif.h for virt board riscv target/riscv: Remove spaces from register names target/riscv: Split gen_arith_imm into functional and temp ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-28Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine Core queue, 2019-05-24 * Display more helpful message when an object type is missing (Philippe Mathieu-Daudé) * Use object_initialize_child for correct reference counting (Philippe Mathieu-Daudé) # gpg: Signature made Fri 24 May 2019 19:31:06 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: hw/intc/nvic: Use object_initialize_child for correct reference counting hw/arm/mps2: Use object_initialize_child for correct reference counting hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting hw/microblaze/zynqmp: Let the SoC manage the IPI devices hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state hw/mips: Use object_initialize_child for correct reference counting hw/mips: Use object_initialize() on MIPSCPSState hw/arm: Use object_initialize_child for correct reference counting hw/arm/aspeed: Use object_initialize_child for correct ref. counting hw/arm/bcm2835: Use object_initialize_child for correct ref. counting hw/arm/bcm2835: Use object_initialize() on PL011State hw/arm/bcm2835: Use TYPE_PL011 instead of hardcoded string hw/virtio: Use object_initialize_child for correct reference counting hw/misc/macio: Use object_initialize_child for correct ref. counting hw/ppc/pnv: Use object_initialize_child for correct reference counting qom/object: Display more helpful message when an object type is missing Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-26BootLinuxSshTest: Test some userspace commands on MaltaPhilippe Mathieu-Daudé
This tests boot a full VM and check the serial console until the SSH daemon is running, then start a SSH session and run some commands. This test can be run using: $ avocado --show=ssh run -t arch:mips tests/acceptance/linux_ssh_mips_malta.py ssh: Entering interactive session. ssh: # uname -a ssh: Linux debian-mips 3.2.0-4-4kc-malta #1 Debian 3.2.51-1 mips GNU/Linux ssh: # lspci -d 11ab:4620 ssh: 00:00.0 Host bridge: Marvell Technology Group Ltd. GT-64120/64120A/64121A System Controller (rev 10) ssh: # cat /sys/bus/i2c/devices/i2c-0/name ssh: SMBus PIIX4 adapter at 1100 ssh: # cat /proc/mtd ssh: dev: size erasesize name ssh: mtd0: 00100000 00010000 "YAMON" ssh: mtd1: 002e0000 00010000 "User FS" ssh: mtd2: 00020000 00010000 "Board Config" ssh: # md5sum /dev/mtd2ro ssh: 0dfbe8aa4c20b52e1b8bf3cb6cbdf193 /dev/mtd2ro ssh: # poweroff Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190523161832.22490-5-f4bug@amsat.org>
2019-05-26target/mips: realign comments to fix checkpatch warningsJules Irenge
Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
2019-05-26target/mips: add or remove space to fix checkpatch errorsJules Irenge
Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>
2019-05-26linux-user: fix __NR_semtimedop undeclared errorLaurent Vivier
In current code, __NR_msgrcv and__NR_semtimedop are supposed to be defined if __NR_msgsnd is defined. But linux headers 5.2-rc1 for MIPS define __NR_msgsnd without defining __NR_semtimedop and it breaks the QEMU build. __NR_semtimedop is defined in asm-mips/unistd_n64.h and asm-mips/unistd_n32.h but not in asm-mips/unistd_o32.h. Commit d9cb4336159a ("linux headers: update against Linux 5.2-rc1") has updated asm-mips/unistd_o32.h and added __NR_msgsnd but not __NR_semtimedop. It introduces __NR_semtimedop_time64 instead. This patch fixes the problem by checking for each __NR_XXX symbol before defining the corresponding syscall. Fixes: d9cb4336159a ("linux headers: update against Linux 5.2-rc1") Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190523175413.14448-1-laurent@vivier.eu>
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář
This commit addresses QEMU Bug #1825311: mips_cpu_handle_mmu_fault renders all accessed pages executable It allows finer-grained control over whether the accessed page should be executable by moving the decision to the underlying map_address function, which has more information for this. As a result, pages that have the XI bit set in the TLB and are accessed for read/write, don't suddenly end up being executable. Fixes: https://bugs.launchpad.net/qemu/+bug/1825311 Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry') Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>
2019-05-26target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic
The old version of the helper for the INSERT.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic
The old version of the helper for the COPY_U.<B|H|W> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic
The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic
Fix the case when the host is a big endian machine, and change the approach toward ST.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic
Fix the case when the host is a big endian machine, and change the approach toward LD.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 255, 256). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic
MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 141, 142). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens
There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip register are read-only." Further, if an interrupt is not delegated to mode x, then "the corresponding bits in xip [...] should appear to be hardwired to zero. This patch implements both of those requirements. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis
Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Revieweb-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Improve the scause logicAlistair Francis
No functional change, just making the code easier to read. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis
The requirement of holding the iothread_mutex is burdersome when swapping the background and foreground registers in the Hypervisor extension. To avoid the requrirement let's set the interrupt asynchronously. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24riscv: spike: Add a generic spike machineAlistair Francis
Add a generic spike machine (not tied to a version) and deprecate the spike mahines that are tied to a specific version. As we can now specify the CPU via the command line we no londer need specific versions of the spike machines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Deprecate the generic no MMU CPUsAlistair Francis
These can now be specified via the command line so we no longer need these. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis
At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24riscv: virt: Allow specifying a CPU via commandlineAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24linux-user/riscv: Add the CPU type as a commentAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens
Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson
These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson
The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson
This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Use pattern groups in insn16.decodeRichard Henderson
This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson
Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Merge argument sets for insn32 and insn16Richard Henderson
In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Use --static-decode for decodetreeRichard Henderson
The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau
This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single stepping handling in places where it was previously ignored such as jalr and system branch instructions (ecall, mret, sret, etc.). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Do not allow sfence.vma from user modeJonathan Behrens
The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau
QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24hw/intc/nvic: Use object_initialize_child for correct reference countingPhilippe Mathieu-Daudé
As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script: @use_sysbus_init_child_obj_missing_parent@ expression child_ptr; expression child_type; expression child_size; @@ - object_initialize(child_ptr, child_size, child_type); ... - qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default()); ... ?- object_unref(OBJECT(child_ptr)); + sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr, + child_size, child_type); We let NVIC adopt the SysTick timer. While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. This choice also matches when using sysbus_init_child_obj(), since its code is: void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); } Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-17-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-24hw/arm/mps2: Use object_initialize_child for correct reference countingPhilippe Mathieu-Daudé
As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script: @use_sysbus_init_child_obj_missing_parent@ expression child_ptr; expression child_type; expression child_size; @@ - object_initialize(child_ptr, child_size, child_type); ... - qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default()); ... ?- object_unref(OBJECT(child_ptr)); + sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr, + child_size, child_type); We let the MPS2 boards adopt the cpu core, the FPGA and the SCC children. While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. This choice also matches when using sysbus_init_child_obj(), since its code is: void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); } Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-16-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-24hw/microblaze/zynqmp: Use object_initialize_child for correct ref. countingPhilippe Mathieu-Daudé
As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script (with a bit of manual fix-up for overly long lines): @use_object_initialize_child@ expression parent_obj; expression child_ptr; expression child_name; expression child_type; expression child_size; expression errp; @@ ( - object_initialize(child_ptr, child_size, child_type); + object_initialize_child(parent_obj, child_name, child_ptr, child_size, + child_type, &error_abort, NULL); ... when != parent_obj - object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), NULL); ... ?- object_unref(OBJECT(child_ptr)); | - object_initialize(child_ptr, child_size, child_type); + object_initialize_child(parent_obj, child_name, child_ptr, child_size, + child_type, errp, NULL); ... when != parent_obj - object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), errp); ... ?- object_unref(OBJECT(child_ptr)); ) While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-15-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-24hw/microblaze/zynqmp: Use object_initialize_child for correct ref. countingPhilippe Mathieu-Daudé
As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the child object will not be properly cleaned up when the parent gets destroyed. Thus let's use now object_initialize_child() instead to get the reference counting here right. This patch was generated using the following Coccinelle script (then manually modified to use numbered IPI name) @use_sysbus_init_child_obj_missing_parent@ expression child_ptr; expression child_type; expression child_size; @@ - object_initialize(child_ptr, child_size, child_type); ... - qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default()); ... ?- object_unref(OBJECT(child_ptr)); + sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr, + child_size, child_type); We let the SoC adopt the IPI children. While the object_initialize() function doesn't take an 'Error *errp' argument, the object_initialize_child() does. Since this code is used when a machine is created (and is not yet running), we deliberately choose to use the &error_abort argument instead of ignoring errors if an object creation failed. This choice also matches when using sysbus_init_child_obj(), since its code is: void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); } Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-14-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-24hw/microblaze/zynqmp: Let the SoC manage the IPI devicesPhilippe Mathieu-Daudé
The Inter Processor Interrupt is a block part of the SoC, not the "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform Management Unit", Power Domains and Islands). Move the IPI management from the machine to the SoC. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-13-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-05-24hw/microblaze/zynqmp: Move the IPI state into the PMUSoC statePhilippe Mathieu-Daudé
The Inter Processor Interrupt is a block part of the SoC, not the "machine" (talking about machine is borderline with the PMU, since it is embedded into the ZynqMP SoC, but currentl QEMU doesn't support multi-arch cores). Move the IPI state to the SoC state, this will simplify the review of the next patch. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190507163416.24647-12-philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-09 15:03:11 +0000