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2023-11-07docs/about/deprecated: Document RISC-V "pmu-num" deprecationRob Bradford
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford
2023-11-07target/riscv: Use existing PMU counter mask in FDT generationRob Bradford
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford
2023-11-07target/riscv: Propagate error from PMU setupRob Bradford
2023-11-07target/riscv: cpu: Set the OpenTitan priv to 1.12.0Alistair Francis
2023-11-07hw/ssi: ibex_spi_host: Clear the interrupt even if disabledAlistair Francis
2023-11-07disas/riscv: Replace TABs with spaceMax Chou
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou
2023-11-07disas/riscv: Add rv_fmt_vd_vs2_uimm formatMax Chou
2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou
2023-11-07MAINTAINERS: update mail address for Weiwei LiWeiwei Li
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt
2023-11-07target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapotDaniel Henrique Barboza
2023-11-07target/riscv/kvm: add zihpm regDaniel Henrique Barboza
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza
2023-11-07target/riscv/kvm: add zicntr regDaniel Henrique Barboza
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza
2023-11-07target/riscv: pmp: Ignore writes when RW=01Mayuresh Chitale
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan
2023-11-07target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansionDaniel Henrique Barboza
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza
2023-11-07target/riscv: handle custom props in qmp_query_cpu_model_expansionDaniel Henrique Barboza
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza
2023-11-07qapi,risc-v: add query-cpu-model-expansionDaniel Henrique Barboza
2023-11-07target/riscv/kvm/kvm-cpu.c: add missing property getters()Daniel Henrique Barboza
2023-11-07docs/system/riscv: update 'virt' machine core limitDaniel Henrique Barboza
2023-11-07linux-user/riscv: change default cpu to 'max'Daniel Henrique Barboza
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal
2023-11-07target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal
2023-11-07target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza
2023-11-07target/riscv: rename ext_ifencei to ext_zifenceiDaniel Henrique Barboza
2023-11-06Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
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