Age | Commit message (Expand) | Author |
2019-09-05 | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 load/store (register offset) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson |
2019-09-05 | target/arm: Add skeleton for T16 decodetree | Richard Henderson |
2019-09-05 | target/arm: Simplify disas_arm_insn | Richard Henderson |
2019-09-05 | target/arm: Simplify disas_thumb2_insn | Richard Henderson |
2019-09-05 | target/arm: Convert TT | Richard Henderson |
2019-09-05 | target/arm: Convert SG | Richard Henderson |
2019-09-05 | target/arm: Convert Table Branch | Richard Henderson |
2019-09-05 | target/arm: Convert Unallocated memory hint | Richard Henderson |
2019-09-05 | target/arm: Convert PLI, PLD, PLDW | Richard Henderson |
2019-09-05 | target/arm: Convert SETEND | Richard Henderson |
2019-09-05 | target/arm: Convert CPS (privileged) | Richard Henderson |
2019-09-05 | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson |
2019-09-05 | target/arm: Convert RFE and SRS | Richard Henderson |
2019-09-05 | target/arm: Convert SVC | Richard Henderson |
2019-09-05 | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson |
2019-09-05 | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson |
2019-09-05 | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson |
2019-09-05 | target/arm: Diagnose writeback register in list for LDM for v7 | Richard Henderson |
2019-09-05 | target/arm: Convert LDM, STM | Richard Henderson |
2019-09-05 | target/arm: Convert MOVW, MOVT | Richard Henderson |
2019-09-05 | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson |
2019-09-05 | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson |
2019-09-05 | target/arm: Convert Parallel addition and subtraction | Richard Henderson |
2019-09-05 | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson |
2019-09-05 | target/arm: Diagnose UNPREDICTABLE ldrex/strex cases | Richard Henderson |
2019-09-05 | target/arm: Convert Synchronization primitives | Richard Henderson |
2019-09-05 | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson |
2019-09-05 | target/arm: Convert T32 ADDW/SUBW | Richard Henderson |
2019-09-05 | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson |
2019-09-05 | target/arm: Convert ERET | Richard Henderson |
2019-09-05 | target/arm: Convert CLZ | Richard Henderson |
2019-09-05 | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson |
2019-09-05 | target/arm: Convert Cyclic Redundancy Check | Richard Henderson |
2019-09-05 | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson |
2019-09-05 | target/arm: Convert MSR (immediate) and hints | Richard Henderson |
2019-09-05 | target/arm: Simplify op_smlawx for SMLAW* | Richard Henderson |
2019-09-05 | target/arm: Simplify op_smlaxxx for SMLAL* | Richard Henderson |
2019-09-05 | target/arm: Convert Halfword multiply and multiply accumulate | Richard Henderson |
2019-09-05 | target/arm: Convert Saturating addition and subtraction | Richard Henderson |
2019-09-05 | target/arm: Simplify UMAAL | Richard Henderson |
2019-09-05 | target/arm: Convert multiply and multiply accumulate | Richard Henderson |
2019-09-05 | target/arm: Convert Data Processing (immediate) | Richard Henderson |
2019-09-05 | target/arm: Convert Data Processing (reg-shifted-reg) | Richard Henderson |
2019-09-05 | target/arm: Convert Data Processing (register) | Richard Henderson |
2019-09-05 | target/arm: Add stubs for aa32 decodetree | Richard Henderson |
2019-09-05 | target/arm: Use store_reg_from_load in thumb2 code | Richard Henderson |
2019-09-05 | qemu-doc: Do not hard-code the name of the QEMU binary | Thomas Huth |