aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-10-04target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6Peter Maydell
In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking branch, so the computed new value is written to r15 as a normal value. The architecture says that in this case, bits [1:0] of the value written must be ignored if we are in ARM mode (or bit [0] ignored if in Thumb mode); this is a change from the ARMv4/v5 specification that behaviour is UNPREDICTABLE. Use the correct mask on the PC value when doing a non-interworking store to PC. A popular library used on RaspberryPi uses this instruction as part of a trick to determine whether it is running on ARMv6 or ARMv7, and we were mishandling the sequence. Fixes bug: https://bugs.launchpad.net/bugs/1625295 Reported-by: <stu.axon@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
2016-10-04target-arm: A64: Fix decoding of iss_sf in disas_ld_litEdgar E. Iglesias
Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04cadence_gem: Fix priority queue out of bounds accessAlistair Francis
There was an error with some of the register implementation assuming there are 16 priority queues supported when the IP only supports 8. This patch corrects the registers to only support 8 queues. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04docs: Add a generic loader explanation documentAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04generic-loader: Add a generic loaderAlistair Francis
Add a generic loader to QEMU which can be used to load images or set memory values. Internally inside QEMU this is a device. It is a strange device that provides no hardware interface but allows QEMU to monkey patch memory specified when it is created. To be able to do this it has a reset callback that does the memory operations. This device allows the user to monkey patch memory. To be able to do this it needs a backend to manage the datas, the same as other memory-related devices. In this case as the backend is so trivial we have merged it with the frontend instead of creating and maintaining a seperate backend. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT tableShannon Zhao
If GIC ITS is supported, add description in ACPI MADT table, then guest could use ITS when booting with ACPI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04ACPI: Add GIC Interrupt Translation Service Structure definitionShannon Zhao
ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure. Here we add the definition of the Structure. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04arm/virt: Add ITS to the virt boardPavel Fedin
If supported by the configuration, ITS will be added automatically. This patch also renames v2m_phandle to msi_phandle because it's now used by both MSI implementations. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulationPavel Fedin
The ITS control frame is in-kernel emulated while accesses to the GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI direct MSI injection advertised by the CAP_SIGNAL_MSI capability) the kvm_gsi_direct_mapping is explicitly set to false to emphasize the difference with GICv2M. Direct mapping cannot work with ITS since the content of the MSI data is not the target interrupt ID but an eventd id. GSI routing is advertised (kvm_gsi_routing_allowed) as well as msi/irqfd signaling (kvm_msi_via_irqfd_allowed). The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI ioctl. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04kvm-all: Pass requester ID to MSI routing functionsPavel Fedin
Introduce global kvm_msi_use_devid flag plus associated kvm_msi_devid_required() macro. Passes the device ID, if needed, while building the MSI route entry. Device IDs are required by the ARM GICv3 ITS (IRQ remapping function is based on this information). Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04target-arm: move gicv3_class_name from machine to kvm_arm.hEric Auger
Machine.c contains code related to migration. Let's move gicv3_class_name to kvm_arm.h instead. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gicv3_its: Implement ITS base classPavel Fedin
This is the basic skeleton for both KVM and software-emulated ITS. Since we already prepare status structure, we also introduce complete VMState description. But, because we currently have no migratable implementations, we also set unmigratable flag. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gic(v3)_kvm: Initialize gsi routingEric Auger
Advertise gsi routing and set up irqchip routing entries for GIC SPIs. This is not mandated as long as MSI routing is not used (because the kernel sets a default irqchip routing table). However once MSI routing gets used (for VIRTIO-PCI vhost for example), the first call to KVM_SET_GSI_ROUTING overrides the kernel default irqchip table. If no routing entry exists for the GSI, any IRQFD signaling for this GSI will fail. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/arm/virt: add 2.8 machine typeAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1474641676-25017-1-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04vmstateify tsc210xDr. David Alan Gilbert
I'm now saving all 3 of the pll entries; only 2 were saved before. There are a couple of times that were previously stored as offsets from 'now' calculated before saving; with vmstate it's easier to store the 'now' and fix it up on reload. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1474977735-10156-3-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04vmstateify tsc2005Dr. David Alan Gilbert
I've converted the fields in it's main data structure to fixed size types in ways that look sane. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1474977735-10156-2-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/arm: Fix Integrator/CM initializationJakub Jermar
Initialization of a class instance cannot depend on its own properties as these are not yet set. Move parts of integratorcm_init() that depend on the "memsz" property to the newly added integratorcm_realize(). This fixes: https://bugs.launchpad.net/qemu/+bug/1624726 Signed-off-by: Jakub Jermar <jakub@jermar.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04mainstone: Add mapping for dot, slash and backspace.Vijay Kumar B
Add missed out mappings. These mappings are from the "Intel PXA27x Processor Developer's Kit User Guide". Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com> Reviewed-by: Deepak S. <deepak@zilogic.com> Message-id: 1475063033-8176-3-git-send-email-vijaykumar@zilogic.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04mainstone: Fix incorrect key mapping for Enter key.Vijay Kumar B
According to the manual the (5, 5) corresponds to backspace key, and not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up to match the mapping in the Linux kernel. Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com> Reviewed-by: Deepak S. <deepak@zilogic.com> Message-id: 1475063033-8176-2-git-send-email-vijaykumar@zilogic.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04MAINTAINERS: Add Alistair to the maintainers listAlistair Francis
Add Alistair Francis as the maintainer for the Netduino 2 and SMM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5a46ccf398b050a41cc3b3d0e94bcff4ce2d85e0.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F205: Connect the SPI devicesAlistair Francis
Connect the SPI devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F205: Connect the ADC devicesAlistair Francis
Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis <alistair@alistair23.me> Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04irq: Add a new irq device that allows the ORing of linesAlistair Francis
Signed-off-by: Alistair Francis <alistair@alistair23.me> Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F2xx: Add the SPI deviceAlistair Francis
Add the STM32F2xx SPI device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F2xx: Add the ADC deviceAlistair Francis
Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F2xx: Display PWM duty cycle from timerAlistair Francis
If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cdb59039a25e061615713a94b40797baa12ea9f9.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F205: Remove the individual device variablesAlistair Francis
Cleanup the individual DeviceState and SysBusDevice variables to re-use the same variable for each device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fc5d75a57d320b69704df2c1146ff0fd482e4a88.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell
staging x86 bug fixes Fix for a XSAVE regression when using "-cpu host", and a fix on the Opteron_G3 CPU model. # gpg: Signature made Mon 03 Oct 2016 20:08:13 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: target-i386: Correct family/model/stepping for Opteron_G3 target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04Merge remote-tracking branch 'remotes/famz/tags/for-upstream' into stagingPeter Maydell
# gpg: Signature made Sun 02 Oct 2016 02:49:58 BST # gpg: using RSA key 0xCA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/for-upstream: docker: Build in a clean directory smbios: fix uuid copy xenpv: Fix qemu_uuid compiling error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-03target-i386: Correct family/model/stepping for Opteron_G3Evgeny Yakovlev
Current CPU definition for AMD Opteron third generation includes features like SSE4a and LAHF_LM support in emulated CPUID. These features are present in K8 rev.E or K10 CPUs and later. However, current G3 family and model describe 2nd generation K8 cores instead. This is incorrect but was considered harmless until our tests found a problem with linux kernels >= 3.10 (and maybe earlier) which specifically check for Opteron K8 model when parsing CPUID leaf 0x80000001: http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c?v=3.16#L552 This code will disable LAHF_LM feature in /proc/cpuinfo if model number is inconsistent. This change sets Opteron_G3 family/model/stepping to 16/2/3 which is a proper Opteron 3rd generation 2350 CPU. Signed-off-by: Evgeny Yakovlev <eyakovlev@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-10-03target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratableEduardo Habkost
A regression was introduced by commit 96193c22a "target-i386: Move xsave component mask to features array": all CPUID[EAX=0xD,ECX=0]:EAX bits were being reported as unmigratable because they don't have feature names defined. This broke "-cpu host" because it enables only migratable features by default. This adds a new field to FeatureWordInfo: migratable_flags, which will make those features be reported as migratable even if they don't have a property name defined. Reported-by: Wanpeng Li <wanpeng.li@hotmail.com> Cc: Paolo Bonzini <bonzini@gnu.org> Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-10-02docker: Build in a clean directoryFam Zheng
Currently we configure and build under "$QEMU_SRC/tests/docker" which is dubious. Create a fixed directory (to be friendly to ccache) and change to there before calling build_qemu. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <1475047892-11955-1-git-send-email-famz@redhat.com>
2016-09-30Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into ↵Peter Maydell
staging Couple of s390x patches: - some PCI cleanups - fix build error due to uuid rework - fix potential deadlock in sigp handling - enable ccw devices in BIOS and enforce checking in QEMU # gpg: Signature made Wed 28 Sep 2016 12:27:03 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20160927: s390x/kvm: fix build against qemu_uuid s390x/css: {c,h,t,r,x}sch: require enable AND device number valid pc-bios/s390-ccw.img: rebuild image pc-bios/s390-ccw: enable subchannel for IPL I/O devices s390x/kvm: Fix potential deadlock in sigp handling s390x/pci: code cleanup s390x/pci: assign msix io region for each pci device s390x/pci: re-arrange variable declarations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-30Merge remote-tracking branch 'remotes/yongbok/tags/mips-20160929' into stagingPeter Maydell
MIPS patches 2016-09-29 Changes: * MIPS Maintainer update * vmstateify rc4030 # gpg: Signature made Thu 29 Sep 2016 13:09:09 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20160929: hw/dma: vmstateify rc4030 MAINTAINERS: update target-mips maintainers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-30Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into stagingPeter Maydell
# gpg: Signature made Thu 29 Sep 2016 21:13:46 BST # gpg: using RSA key 0x7DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: ide: Fix memory leak in ide_register_restart_cb() MAINTAINERS: Add some more headers to the IDE section ahci: clear aiocb in ncq_cb ide: fix DMA register transitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-29ide: Fix memory leak in ide_register_restart_cb()Ashijeet Acharya
Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add idebus_unrealize() in hw/ide/qdev.c to have calls to qemu_del_vm_change_state_handler() to deal with the dangling change state handler during hot-unplugging ide devices which might lead to a crash. Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1474995212-10580-1-git-send-email-ashijeetacharya@gmail.com [Minor whitespace fix --js] Signed-off-by: John Snow <jsnow@redhat.com>
2016-09-29MAINTAINERS: Add some more headers to the IDE sectionThomas Huth
The folder include/hw/ide/ belongs to the IDE section. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-id: 1474646996-30421-1-git-send-email-thuth@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2016-09-29ahci: clear aiocb in ncq_cbJohn Snow
Similar to existing fixes for IDE (87ac25fd) and ATAPI (7f951b2d), the AIOCB must be cleared in the callback. Otherwise, we may accidentally try to reset a dangling pointer in bdrv_aio_cancel() from a port reset. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1474575040-32079-2-git-send-email-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2016-09-29ide: fix DMA register transitionsJohn Snow
ATA8-APT defines the state transitions for both a host controller and for the hardware device during the lifecycle of a DMA transfer, in section 9.7 "DMA command protocol." One of the interesting tidbits here is that when a device transitions from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer State"), it can choose to set either BSY or DRQ to signal this transition, but not both. as ide_sector_dma_start is the last point in our preparation process before we begin the real data transfer process (for either AHCI or BMDMA), this is the correct transition point for DDMA0 to DDMA1. I have chosen !BSY && DRQ for QEMU to make the transition from DDMA0 the most obvious. Reported-by: Benjamin David Lunt <fys@fysnet.net> Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Tested-by: Stefan Weil <sw@weilnetz.de> Message-id: 1470175541-19344-1-git-send-email-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2016-09-29hw/dma: vmstateify rc4030Dr. David Alan Gilbert
Convert rc4030 to VMState. Now saving the whole 16 entries rather than 15. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Tested-by: Hervé Poussineau <hpoussin@reactos.org> [Yongbok Kim: edited commit message] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2016-09-29MAINTAINERS: update target-mips maintainersLeon Alrae
Yongbok Kim takes over the target-mips maintenance from me. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2016-09-29smbios: fix uuid copyMarc-André Lureau
Since 9c5ce8db, the uuid is wrongly copied, as QemuUUID 'in' argument is already a pointer. Fixes ASAN complaining: hw/smbios/smbios.c:489:5: runtime error: load of address 0x7fffcdb91b00 with insufficient space for an object of type '__int128 unsigned' Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20160928143810.25558-1-marcandre.lureau@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [Warp the long error message line in commit message. - Fam] Signed-off-by: Fam Zheng <famz@redhat.com>
2016-09-29xenpv: Fix qemu_uuid compiling errorFam Zheng
9c5ce8db2 switched the type of qemu_uuid and this should have followed. Fix it. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <1474968011-29382-1-git-send-email-famz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
2016-09-29Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Wed 28 Sep 2016 22:30:45 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace: Document the execution mode of guest events trace: Add event "guest_cpu_reset" trace: Add event "guest_cpu_enter" trace: Properly initialize dynamic event states in hot-plugged vCPUs trace: move hw/virtio/virtio-balloon.c trace points into correct file trace: move hw/mem/pc-dimm.c trace points into correct file trace: move util/qemu-coroutine*.c trace points into correct file trace: move util/buffer.c trace points into correct file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* thread-safe tb_flush (Fred, Alex, Sergey, me, Richard, Emilio,... :-) * license clarification for compiler.h (Felipe) * glib cflags improvement (Marc-André) * checkpatch silencing (Paolo) * SMRAM migration fix (Paolo) * Replay improvements (Pavel) * IOMMU notifier improvements (Peter) * IOAPIC now defaults to version 0x20 (Peter) # gpg: Signature made Tue 27 Sep 2016 10:57:40 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (28 commits) replay: allow replay stopping and restarting replay: vmstate for replay module replay: move internal data to the structure cpus-common: lock-free fast path for cpu_exec_start/end tcg: Make tb_flush() thread safe cpus-common: Introduce async_safe_run_on_cpu() cpus-common: simplify locking for start_exclusive/end_exclusive cpus-common: remove redundant call to exclusive_idle() cpus-common: always defer async_run_on_cpu work items docs: include formal model for TCG exclusive sections cpus-common: move exclusive work infrastructure from linux-user cpus-common: fix uninitialized variable use in run_on_cpu cpus-common: move CPU work item management to common code cpus-common: move CPU list management to common code linux-user: Add qemu_cpu_is_self() and qemu_cpu_kick() linux-user: Use QemuMutex and QemuCond cpus: Rename flush_queued_work() cpus: Move common code out of {async_, }run_on_cpu() cpus: pass CPUState to run_on_cpu helpers build-sys: put glib_cflags in QEMU_CFLAGS ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-28Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging # gpg: Signature made Wed 28 Sep 2016 19:15:22 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: linux-aio: fix re-entrant completion processing test-coroutine: test qemu_coroutine_entered() coroutine: add qemu_coroutine_entered() function libqos: fix qvring_init() iothread: check iothread->ctx before aio_context_unref to avoid assertion aio-posix: avoid unnecessary aio_epoll_enabled() calls block: mirror: fix wrong comment of mirror_start Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-28trace: Document the execution mode of guest eventsLluís Vilanova
Explicitly state in which execution mode (user, softmmu, all) are guest events available for tracing. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 147456962135.11114.6146034359114598596.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-09-28trace: Add event "guest_cpu_reset"Lluís Vilanova
Signals the reset of the state a virtual (guest) CPU. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 147428971851.15111.8799439252178273840.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-09-28trace: Add event "guest_cpu_enter"Lluís Vilanova
Signals the hot-plugging of a new virtual (guest) CPU. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 147428971313.15111.18023030883528426840.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-09-28trace: Properly initialize dynamic event states in hot-plugged vCPUsLluís Vilanova
Every time a vCPU is hot-plugged, it will "inherit" its tracing state from the global state array. That is, if *any* existing vCPU has an event enabled, new vCPUs will have too. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 147428970768.15111.7664565956870423529.stgit@fimbulvetr.bsc.es Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-04 10:58:31 +0000