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2014-02-11exec: On AS changes, only flush affected CPU TLBsEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11cpu: Add per-cpu address spaceEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11memory: Add MemoryListener to typedefs.hEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make memory_region_section_get_iotlb use section ASEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Always initialize MemorySection address spacesEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make iotlb_to_region input an ASEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias
No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140208' into staging target-arm queue: * more A64 Neon instructions * AArch32 VCVTB and VCVTT ARMv8 instructions * fixes to inaccuracies in GIC emulation * libvixl disassembler for A64 * Allwinner SoC ethernet controller * zynq software system reset support # gpg: Signature made Sat 08 Feb 2014 15:53:05 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140208: (29 commits) arm/zynq: Add software system reset via SCLR hw/arm/allwinner-a10: initialize EMAC hw/net: add support for Allwinner EMAC Fast Ethernet controller util/fifo8: clear fifo head upon reset util/fifo8: implement push/pop of multiple bytes disas: Implement disassembly output for A64 disas/libvixl: Fix upstream libvixl compilation issues disas: Add subset of libvixl sources for A64 disassembler rules.mak: Link with C++ if we have a C++ compiler rules.mak: Support .cc as a C++ source file suffix arm_gic: Add GICC_APRn state to the GICState vmstate: Add uint32 2D-array support arm_gic: Support setting/getting binary point reg arm_gic: Keep track of SGI sources arm_gic: Fix GIC pending behavior target-arm: Add support for AArch32 64bit VCVTB and VCVTT target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group target-arm: A64: Add 2-reg-misc REV* instructions target-arm: A64: Add narrowing 2-reg-misc instructions target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-10Merge remote-tracking branch 'remotes/kvaneesh/for-upstream' into stagingPeter Maydell
* remotes/kvaneesh/for-upstream: hw/9pfs: fix P9_STATS_GEN handling hw/9pfs: make get_st_gen() return ENOTTY error on special files hw/9pfs: handle undefined FS_IOC_GETVERSION case in handle_ioc_getversion() hw/9pfs: fix error handing in local_ioc_getversion() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-10memory: fix limiting of translation at a page boundaryPaolo Bonzini
Commit 360e607 (address_space_translate: do not cross page boundaries, 2014-01-30) broke MMIO accesses in cases where the section is shorter than the full register width. This can happen for example with the Bochs DISPI registers, which are 16 bits wide but have only a 1-byte long MemoryRegion (if you write to the "second byte" of the register your access is discarded; it doesn't write only to half of the register). Restrict the action of commit 360e607 to direct RAM accesses. This is enough for Xen, since MMIO will not go through the mapcache. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08Merge remote-tracking branch 'remotes/mwalle/tags/lm32-fixes/20140204' into ↵Peter Maydell
staging target-lm32: fixes # gpg: Signature made Tue 04 Feb 2014 18:47:56 GMT using DSA key ID 3F98A378 # gpg: Can't check signature: public key not found * remotes/mwalle/tags/lm32-fixes/20140204: hw/lm32: print error if cpu model is not found target-lm32: stop VM on illegal or unknown instruction lm32_sys: dump cpu state if test case fails lm32_sys: print test result on stderr target-lm32: add breakpoint/watchpoint support target-lm32: move model features to LM32CPU target-lm32: kill cpu_abort() calls milkymist-vgafb: swap pixel data in source buffer lm32_uart/lm32_juart: use qemu_chr_fe_write_all() milkymist-uart: use qemu_chr_fe_write_all() instead of qemu_chr_fe_write() tests: lm32: new rule for single test cases lm32_sys: increase test case name length limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm/zynq: Add software system reset via SCLRSebastian Huber
Support software-driven system reset via the register in the SCLR. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08hw/arm/allwinner-a10: initialize EMACBeniamino Galvani
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08hw/net: add support for Allwinner EMAC Fast Ethernet controllerBeniamino Galvani
This patch adds support for the Fast Ethernet MAC found on Allwinner SoCs, together with a basic emulation of Realtek RTL8201CP PHY. Since there is no public documentation of the Allwinner controller, the implementation is based on Linux kernel driver. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08util/fifo8: clear fifo head upon resetBeniamino Galvani
To improve the predictability of fifo8_pop_buf(), the fifo head is set to the start of data buffer upon a reset so that the first call to the function will be able to retrieve all data in the fifo. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08util/fifo8: implement push/pop of multiple bytesBeniamino Galvani
The patch adds functions fifo8_push_all() and fifo8_pop_buf() which can be used respectively to push the content of a memory buffer to the fifo and to pop multiple bytes obtaining a pointer to the fifo backing buffer. In addition, it implements fifo8_num_free() and fifo8_num_used() which allow to check if a multi-byte operation can be performed. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
Use libvixl to implement disassembly output in debug logs for A64, for use with both AArch64 hosts and targets. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: * added support for target disassembly * switched to custom QEMUDisassembler so the output format matches what QEMU expects * make sure we correctly fall back to "just print hex" if we didn't build the AArch64 disassembler because of lack of a C++ compiler * rename from 'aarch64' to 'arm-a64' because this is a disassembler for the A64 instruction set * merge aarch64.c and aarch64-cxx.cc into one C++ file * simplify the aarch64.c<->aarch64-cxx.cc interface] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08disas/libvixl: Fix upstream libvixl compilation issuesPeter Maydell
Fix various minor issues with upstream libvixl so that it will compile successfully on the platforms QEMU cares about: * remove unused GBytes constant (it clashes with the glib headers) * fix suffixes on constants to use 'LL' for 64 bit constants so we can compile on 32 bit hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08disas: Add subset of libvixl sources for A64 disassemblerPeter Maydell
Add the subset of the libvixl sources that are needed for the A64 disassembler support. These sources come from https://github.com/armvixl/vixl commit 578645f14e122d2b which is VIXL release 1.1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08rules.mak: Link with C++ if we have a C++ compilerPeter Maydell
If we have a C++ compiler available, link with it, because we might be linking some C++ files in. This allows us to include C++ object files in the QEMU binary proper. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08rules.mak: Support .cc as a C++ source file suffixPeter Maydell
The A64 disassembler libvixl uses .cc as its suffix for C++ source files, so add support for it (we already support .cpp). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08arm_gic: Add GICC_APRn state to the GICStateChristoffer Dall
The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08vmstate: Add uint32 2D-array supportChristoffer Dall
Add support for saving VMState of 2D arrays of uint32 values. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Support setting/getting binary point regChristoffer Dall
Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Keep track of SGI sourcesChristoffer Dall
Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always). Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ and make the state visible to the guest. Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Fix GIC pending behaviorChristoffer Dall
The existing implementation of the pending behavior in gic_set_irq, gic_complete_irq, and the distributor pending set/clear registers does not follow the semantics of the GICv2.0 specs, but may implement the 11MPCore support. Therefore, maintain the existing semantics for 11MPCore and v7M NVIC and change the behavior to be in accordance with the GICv2.0 specs for "generic implementations" (s->revision == 1 || s->revision == 2). Generic implementations distinguish between setting a level-triggered interrupt pending through writes to the GICD_ISPENDR and when hardware raises the interrupt line. Writing to the GICD_ICPENDR will not cause the interrupt to become non-pending if the line is still active, and conversely, if the line is deactivated but the interrupt is marked as pending through a write to GICD_ISPENDR, the interrupt remains pending. Handle this situation in the GIC_TEST_PENDING (which now becomes a static inline named gic_test_pending) and let the 'pending' field correspond only to the latched state of the D-flip flop in the GICv2.0 specs Figure 4-10. The following changes are added: gic_test_pending: Make this a static inline and split out the 11MPCore from the generic behavior. For the generic behavior, consider interrupts pending if: ((s->irq_state[irq].pending & (cm) != 0) || (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)) gic_set_irq: Split out the 11MPCore from the generic behavior. For the generic behavior, always GIC_SET_LEVEL() on positive level, but only GIC_SET_PENDING for edge-triggered interrupts and always simply GIC_CLEAR_LEVEL() on negative level. gic_complete_irq: Only resample the line for line-triggered interrupts on an 11MPCore. Generic implementations will sample the line directly in gic_test_pending(). Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton
Add support for the AArch32 floating-point half-precision to double- precision conversion VCVTB and VCVTT instructions. Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: fixed a minor missing-braces style issue] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée
Add the byte-reverse operations REV64, REV32 and REV16 from the two-reg-misc group. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell
Add the narrowing integer instructions in the 2-reg-misc class. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell
Implement the simple 2-register-misc operations we can share with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS, SQNEG also fall into this category, but aren't implemented in the scalar-2-register case yet either.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell
Add a skeleton decode for the SIMD 2-reg misc group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell
Implement the simple 64 bit integer operations from the SIMD scalar 2-register misc group (C3.6.12): the comparisons against zero, plus ABS and NEG. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell
Implement the remaining integer instructions in the scalar-three-reg-same group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL, SQDMULH, SQRDMULH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell
Implement the instructions in the scalar pairwise group (C3.6.8). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTRPeter Maydell
We have macros for marking TCGv values as unused, checking if they are unused and comparing them to each other. However these only exist for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell
Implement the pairwise integer operations in the 3-reg-same SIMD group: ADDP, SMAXP, SMINP, UMAXP and UMINP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell
Implement the SIMD 3-reg-same instructions where the size == 3 case is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX, UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL, SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.) This completes the non-pairwise integer instructions in this category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell
Implement the SIMD 3-reg-same instructions SQADD, UQADD, SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL, SQRSHL, UQRSHL; these are all simple calls to existing Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL for the 3-reg-same-scalar category (but not the others because they can have non-size-64 operands and the scalar_3reg_same function doesn't support that yet.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08Merge remote-tracking branch ↵Peter Maydell
'remotes/juanquintela/tags/migration/20140204-1' into staging migration/next for 20140204 # gpg: Signature made Tue 04 Feb 2014 15:52:00 GMT using RSA key ID 5872D723 # gpg: Can't check signature: public key not found * remotes/juanquintela/tags/migration/20140204-1: Don't abort on memory allocation error Don't abort on out of memory when creating page cache XBZRLE cache size should not be larger than guest memory size migration:fix free XBZRLE decoded_buf wrong Add check for cache size smaller than page size Set xbzrle buffers to NULL after freeing them to avoid double free errors exec: fix ram_list dirty map optimization vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-type Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-07Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-1' into stagingPeter Maydell
Update seabios to 1.7.4 # gpg: Signature made Mon 03 Feb 2014 14:42:44 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-roms-1: Update seabios binaries to 1.7.4 Update seabios submodule to 1.7.4 roms: remove explicit MAKEFLAGS from recursive make invocations Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-07Merge remote-tracking branch 'remotes/stefanha/tags/qtest-for-peter' into ↵Peter Maydell
staging qtest resource cleanup patches # gpg: Signature made Tue 04 Feb 2014 08:29:12 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/qtest-for-peter: qtest: unlink UNIX domain sockets after connecting qtest: unlink QEMU pid file after startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-06Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell
* remotes/kvm/uq/master: target-i386: Move KVM default-vendor hack to instance_init target-i386: Don't change x86_def_t struct on cpu_x86_register() target-i386: Eliminate CONFIG_KVM #ifdefs kvm: add support for hyper-v timers kvm: make hyperv vapic assist page migratable kvm: make hyperv hypercall and guest os id MSRs migratable. kvm: make availability of Hyper-V enlightenments dependent on KVM_CAP_HYPERV KVM: fix coexistence of KVM and Hyper-V leaves kvm: print suberror on all internal errors target-i386: kvm_check_features_against_host(): Kill feature word array target-i386: kvm_cpu_fill_host(): Fill feature words in a loop target-i386: kvm_cpu_fill_host(): Set all feature words at end of function target-i386: kvm_cpu_fill_host(): No need to check xlevel2 target-i386: kvm_cpu_fill_host(): No need to check CPU vendor target-i386: kvm_cpu_fill_host(): No need to check level target-i386: kvm_cpu_fill_host(): Kill unused code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-06Merge remote-tracking branch 'remotes/spice/tags/pull-spice-2' into stagingPeter Maydell
misc spice patches # gpg: Signature made Mon 03 Feb 2014 15:05:29 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/spice/tags/pull-spice-2: spice: hook qemu_chr_fe_set_open() event to ports Add the ability to vary Spice playback and record rates, to facilitate Opus support. hw/display/qxl: fix signed to unsigned comparison qxl: clear irq on reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-05Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-02-02' ↵Peter Maydell
into staging trivial patches for 2014-02-02 # gpg: Signature made Sun 02 Feb 2014 16:11:37 GMT using RSA key ID 74F0C838 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: E190 8639 3B10 B51B AC2C 8B73 5253 C5AD 74F0 C838 * remotes/mjt/tags/trivial-patches-2014-02-02: tests/.gitignore: Ignore tests/check-qom-interface hw/ppc: Remove unused defines readline: Add missing GCC_FMT_ATTR tcg/s390: Remove sigill_handler i386: Add missing include file for QEMU_PACKED osdep: drop unused #include "trace.h" qemu 1.7.0 does not build on NetBSD Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-05Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Block pull request # gpg: Signature made Fri 31 Jan 2014 21:16:43 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: qemu-iotests: only run 071 on qcow2 dataplane: Comment fix block/vhdx: Error checking fixes qemu-iotests: Drop assert_no_active_commit in case 040 block/vmdk: add basic .bdrv_check support block: remove qcow2 .bdrv_make_empty implementation block: remove QED .bdrv_make_empty implementation Describe flaws in qcow/qcow2 encryption in the docs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-04hw/lm32: print error if cpu model is not foundMichael Walle
QEMU crashed if a the given cpu_model is not found. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-04target-lm32: stop VM on illegal or unknown instructionMichael Walle
Instead of translating the instruction to a no-op, pause the VM and display a message to the user. As a side effect, this also works for instructions where the operands are only known at runtime. Signed-off-by: Michael Walle <michael@walle.cc>
2014-02-04lm32_sys: dump cpu state if test case failsMichael Walle
This will ease debugging the test cases. Signed-off-by: Michael Walle <michael@walle.cc>
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