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2013-07-18target-alpha: Move alarm to vm_clockRichard Henderson
Basing the alarm off the rtc_clock was silly. It leads to horrible spinning in the guest after being suspended and resumed, as it tries to catch up with lost ticks. This requires adding an accessor for reading the vm_clock too. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-15Merge remote-tracking branch 'quintela/migration.next' into stagingAnthony Liguori
# By Chegu Vinod # Via Juan Quintela * quintela/migration.next: Force auto-convegence of live migration Add 'auto-converge' migration capability Introduce async_run_on_cpu() Message-id: 1373664508-5404-1-git-send-email-quintela@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge remote-tracking branch 'cohuck/virtio-ccw-upstr' into stagingAnthony Liguori
# By Dominik Dingel # Via Cornelia Huck * cohuck/virtio-ccw-upstr: virtio-ccw: Enable x-data-plane for virtio-ccw-blk Message-id: 1373903207-27085-1-git-send-email-cornelia.huck@de.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130715-1' into ↵Anthony Liguori
staging target-arm queue # gpg: Signature made Mon 15 Jul 2013 11:15:13 AM CDT using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Mans Rullgard (3) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20130715-1: target-arm: Avoid g_hash_table_get_keys() target-arm: avoid undefined behaviour when writing TTBCR target-arm/helper.c: Allow const opaques in arm CP target-arm/helper.c: Implement MIDR aliases target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup target-arm: explicitly decode SEVL instruction target-arm: implement LDA/STL instructions target-arm: add feature flag for ARMv8 Message-id: 1373905022-27735-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge remote-tracking branch 'pmaydell/tags/pull-arm-devs-20130715' into stagingAnthony Liguori
arm-devs queue # gpg: Signature made Mon 15 Jul 2013 10:53:44 AM CDT using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Peter Maydell (4) and others # Via Peter Maydell * pmaydell/tags/pull-arm-devs-20130715: ARM/highbank: add support for Calxeda ECX-2000 / Midway ARM/highbank: prepare for adding similar machines hw/arm/vexpress: Add alias for flash at address 0 on A15 board hw/dma/omap_dma: Fix bugs with DMA requests above 32 sd/pl181.c: Avoid undefined shift behaviour in RWORD macro hw/cpu/a15mpcore: Correct default value for num-irq char/cadence_uart: Fix reset for unattached instances Message-id: 1373904095-27592-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge remote-tracking branch 'rth/axp-next' into stagingAnthony Liguori
# By Richard Henderson # Via Richard Henderson * rth/axp-next: hw/alpha: Use SRM epoch hw/alpha: Drop latch_tmp hack exec: Support 64-bit operations in address_space_rw hw/alpha: Don't machine check on missing pci i/o hw/alpha: Don't use get_system_io Message-id: 1373840171-25556-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori
# By Kevin Wolf (6) and Stefan Hajnoczi (2) # Via Kevin Wolf * kwolf/for-anthony: ahci: Fix FLUSH command migration: Fail migration on bdrv_flush_all() error cpus: Add return value for vm_stop() block: Add return value for bdrv_flush_all() qemu-iotests: Update 051 reference output block: Don't parse protocol from file.filename block: add drive_backup HMP command blockdev: add sync mode to drive-backup QMP command Message-id: 1373887000-4488-1-git-send-email-kwolf@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15target-arm: Avoid g_hash_table_get_keys()Peter Maydell
g_hash_table_get_keys() was only introduced in glib 2.14, and we're still targeting a minimum version of 2.12. Rewrite the offending code (introduced in commit 721fae1) to use g_hash_table_foreach() to build the list of keys. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1372678819-8633-1-git-send-email-peter.maydell@linaro.org
2013-07-15target-arm: avoid undefined behaviour when writing TTBCRPeter Maydell
LPAE CPUs have more potentially valid bits in the TTBCR, and so the simple masking out of invalid bits is no longer sufficient to obtain the base address width field of the register, which is what we use to precalculate c2_mask and c2_base_mask. Explicitly extract the relevant register field rather than simply shifting by the register value. This bug would have had no ill effects in practice, since if the EAE bit (TTBCR bit 31) is set then we don't use the precalculated masks, and if EAE is zero then bits 30..3 are all UNK/SBZP, so well-behaved guests won't set them. However the shift is undefined behaviour, so we should avoid it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1372347527-4428-1-git-send-email-peter.maydell@linaro.org
2013-07-15target-arm/helper.c: Allow const opaques in arm CPPeter Crosthwaite
Allow for defining const opaque data in ARM CP register definitions by setting .opaque = foo. If non null opaque is passed into define_one_arm_cp_reg_with_opaque then that opaque will take precedence, otherwise if null opaque is passed, the original opaque data will be used. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: cf0a3ac3438d97464240db9f5f4ef1585cbc1d77.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm/helper.c: Implement MIDR aliasesPeter Crosthwaite
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space default to aliasing the MIDR register. Set all registers in the space to access MIDR by default. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 6127846712b7ad2727354a4f5e1d809451f1e859.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanupPeter Crosthwaite
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo .access fields in place. So there is no need to replicate the call to define_arm_cp_reg(). Dropped, and let the OMAP case fall through to the normal behaviour after the in-place modification. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.1373429432.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm: explicitly decode SEVL instructionMans Rullgard
The ARMv8 SEVL instruction is in the architectural hint space already emulated as nop. This makes the decoding of SEVL explicit for clarity. Signed-off-by: Mans Rullgard <mans@mansr.com> Message-id: 1370606786-5650-3-git-send-email-mans@mansr.com [PMM: added 'SEVL' to the TODO comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15target-arm: implement LDA/STL instructionsMans Rullgard
This adds support for the ARMv8 load acquire/store release instructions. Since qemu does nothing special for memory barriers, these can be emulated like their non-acquire/release counterparts. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15virtio-ccw: Enable x-data-plane for virtio-ccw-blkDominik Dingel
Add property x-data-plane to virtio-ccw-blk devices. Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2013-07-15ARM/highbank: add support for Calxeda ECX-2000 / MidwayAndre Przywara
The Calxeda ECX-2000 chip (aka. Midway) is model-wise quite similar to the Highbank. The most prominent difference is the Cortex-A15 CPU core in it, together with the associated core peripherals. Add a new ARM machine type called "midway". Move the L2 cache controller device into the Highbank specific part, since Midway does not have (and need) it. Signed-off-by: Andre Przywara <andre.przywara@calxeda.com> Message-id: 1373026897-12085-3-git-send-email-andre.przywara@calxeda.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15ARM/highbank: prepare for adding similar machinesAndre Przywara
To allow the modelling of machines similar to Calxeda Highbank, introduce a parameter to the init function and call it from a wrapper. This allows to tweak the definition for individual machines later on. Signed-off-by: Andre Przywara <andre.przywara@calxeda.com> Message-id: 1373026897-12085-2-git-send-email-andre.przywara@calxeda.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15hw/arm/vexpress: Add alias for flash at address 0 on A15 boardPeter Maydell
The A15 Versatile Express board can remap a variety of things at address 0. We don't currently emulate the Serial Configuration Controller which is how the guest can control this remapping, but we can provide the initial default mapping of the first flash device into this space. In particular this allows QEMU to boot flash images such as UEFI which expect to include an exception vector table. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Grant Likely <grant.likely@linaro.org> Message-id: 1373374180-19884-1-git-send-email-peter.maydell@linaro.org
2013-07-15hw/dma/omap_dma: Fix bugs with DMA requests above 32Peter Maydell
The drqbmp field of struct soc_dma_s is a uint64_t; however several places in the code attempt to set bits in it using "(1 << drq)", which will fail if drq is large enough that the 1 bit gets shifted off the top of a 32 bit integer. Change these to "(1ULL << drq)" so that the promotion to 64 bit happens before the shift rather than afterwards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1372423919-5669-1-git-send-email-peter.maydell@linaro.org
2013-07-15sd/pl181.c: Avoid undefined shift behaviour in RWORD macroPeter Maydell
Add a cast to avoid potentially shifting into the sign bit of a signed value, which is undefined behaviour in C. (Detected with clang's -fsanitize=undefined.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1372341831-4264-1-git-send-email-peter.maydell@linaro.org
2013-07-15hw/cpu/a15mpcore: Correct default value for num-irqPeter Maydell
The a15mpcore device claims that its default value for num-irq is the number of interrupts used by the A15MP in the vexpress-a15 board. However that chip has 128 external interrupts, not 64. Since there is only one A15 based model in QEMU currently, we can fix this by simply changing the default value. This error was causing recent (3.10) Linux kernels to print warnings/backtraces when the number of interrupts reported by the GIC was smaller than an interrupt number they wanted to use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1373032481-15280-1-git-send-email-peter.maydell@linaro.org
2013-07-15target-arm: add feature flag for ARMv8Mans Rullgard
Signed-off-by: Mans Rullgard <mans@mansr.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15char/cadence_uart: Fix reset for unattached instancesPeter Crosthwaite
commit 1db8b5efe0c2b5000e50691eea61264a615f43de introduced an issue where QEMU would segfault if you have an unattached Cadence UART. Fix by guarding the flush-on-reset logic on there being a qemu_chr attachment. Reported-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Message-id: 9009578ee10a50d994b2e10aa2840d73765f5968.1370577272.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15ahci: Fix FLUSH commandKevin Wolf
AHCI couldn't cope with asynchronous commands that aren't doing DMA, it simply wouldn't complete them. Due to the bug fixed in commit f68ec837, FLUSH commands would seem to have completed immediately even if they were still running on the host. After the commit, they would simply hang and never unset the BSY bit, rendering AHCI unusable on any OS sending flushes. This patch adds another callback for the completion of asynchronous commands. This is what AHCI really wants to use for its command completion logic rather than an DMA completion callback. Cc: qemu-stable@nongnu.org Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-15migration: Fail migration on bdrv_flush_all() errorKevin Wolf
If bdrv_flush_all() returns an error, there is an inconsistency in the view of an image file between the source and the destination host. Completing the migration would lead to corruption. Better abort migration in this case. To reproduce this case, try the following (ensures that there is something to flush, and then fails that flush): $ qemu-img create -f qcow2 test.qcow2 1G $ cat blkdebug.cfg [inject-error] event = "flush_to_os" errno = "5" $ qemu-system-x86_64 -hda blkdebug:blkdebug.cfg:test.qcow2 -monitor stdio (qemu) qemu-io ide0-hd0 "write 0 4k" (qemu) migrate ... Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-15cpus: Add return value for vm_stop()Kevin Wolf
If flushing the block devices fails, return an error. The VM is stopped anyway. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-15block: Add return value for bdrv_flush_all()Kevin Wolf
bdrv_flush() can fail, and bdrv_flush_all() should return an error as well if this happens for a block device. It returns the first error return now, but still at least tries to flush the remaining devices even in error cases. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-15qemu-iotests: Update 051 reference outputKevin Wolf
This has been broken by commit bd5c51ee. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-07-15block: Don't parse protocol from file.filenameKevin Wolf
One of the major reasons for doing something new for -blockdev and blockdev-add was that the old block layer code parses filenames instead of just taking them literally. So we should really leave it untouched when it's passing using the new interfaces (like -drive file.filename=...). This allows opening relative file names that contain a colon. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2013-07-15block: add drive_backup HMP commandStefan Hajnoczi
Make "drive_backup" available on the HMP monitor: drive_backup [-n] [-f] device target [format] The -n flag requests QEMU to reuse the image found in new-image-file, instead of recreating it from scratch. The -f flag requests QEMU to copy the whole disk, so that the result does not need a backing file. Note that this flag *must* currently be passed since the other sync modes ('none' and 'top') have not been implemented yet. Requiring it ensures that "drive_backup" behaves like "drive_mirror". Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-07-15blockdev: add sync mode to drive-backup QMP commandStefan Hajnoczi
The drive-backup command is similar to the drive-mirror command, except no guest data written after the command executes gets copied. Add a sync mode argument which determines whether the entire disk is copied, just allocated clusters, or only clusters being written to by the guest. Currently only sync mode 'full' is supported - it copies the entire disk. For read-only point-in-time snapshots we may only need sync mode 'none' since the target can be a qcow2 file using the guest's disk as its backing file (no need to copy the entire disk). Finally, sync mode 'top' is useful if we wish to preserve the backing chain. Note that this patch just adds the sync mode argument to drive-backup. It does not implement sync modes 'top' or 'none'. This patch is necessary so we can add a drive-backup HMP command that behaves like the existing drive-mirror HMP command and takes a sync mode. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-07-14hw/alpha: Use SRM epochRichard Henderson
The 1980 epoch is used by the ARC PALcode for NT. But we're emulating a system using the SRM PALcode. Using the proper epoch results in less confusion in the guest userland. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-14hw/alpha: Drop latch_tmp hackRichard Henderson
The memory and i/o core now support passing 64-bit accesses along from the guest, so we no longer need to emulate them. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-14exec: Support 64-bit operations in address_space_rwRichard Henderson
Honor the implementation maximum access size, and at least check the minimum access size. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-13hw/alpha: Don't machine check on missing pci i/oRichard Henderson
Not really correct, but we don't implement all of the random devices that the kernel looks for. This is good enough to keep us booting. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-13hw/alpha: Don't use get_system_ioRichard Henderson
Advancements in the ioport subsystem mean that we need no longer thunk memory-mapped i/o through the system-io address space. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-12ioport: remove LITTLE_ENDIAN mark for portioAnthony Liguori
Setting it to LE forces a byte swap when host != guest endian but this makes no sense at all. Herve made the suggestion upon observing that word writes/reads were broken into byte writes/reads in such a way as to assume devices are interpret registers as LE. However, even if this were a problem, marking the region as LE is not useful because what's essentially happening here is that LE is open coded. So by marking it LE in MemoryRegionOps, we're doing a superflous swap. Now, the portio code is suspicious to begin with. The dispatch layer really has no purpose in splitting I/O requests in the first place... Cc: Hervé Poussineau <hpoussin@reactos.org> Cc: Alex Graf <agraf@suse.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-12Force auto-convegence of live migrationChegu Vinod
If a user chooses to turn on the auto-converge migration capability these changes detect the lack of convergence and throttle down the guest. i.e. force the VCPUs out of the guest for some duration and let the migration thread catchup and help converge. Verified the convergence using the following : - Java Warehouse workload running on a 20VCPU/256G guest(~80% busy) - OLTP like workload running on a 80VCPU/512G guest (~80% busy) Sample results with Java warehouse workload : (migrate speed set to 20Gb and migrate downtime set to 4seconds). (qemu) info migrate capabilities: xbzrle: off auto-converge: off <---- Migration status: active total time: 1487503 milliseconds expected downtime: 519 milliseconds transferred ram: 383749347 kbytes remaining ram: 2753372 kbytes total ram: 268444224 kbytes duplicate: 65461532 pages skipped: 64901568 pages normal: 95750218 pages normal bytes: 383000872 kbytes dirty pages rate: 67551 pages --- (qemu) info migrate capabilities: xbzrle: off auto-converge: on <---- Migration status: completed total time: 241161 milliseconds downtime: 6373 milliseconds transferred ram: 28235307 kbytes remaining ram: 0 kbytes total ram: 268444224 kbytes duplicate: 64946416 pages skipped: 64903523 pages normal: 7044971 pages normal bytes: 28179884 kbytes Signed-off-by: Chegu Vinod <chegu_vinod@hp.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2013-07-12Add 'auto-converge' migration capabilityChegu Vinod
The auto-converge migration capability allows the user to specify if they choose live migration seqeunce to automatically detect and force convergence. Signed-off-by: Chegu Vinod <chegu_vinod@hp.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2013-07-12Introduce async_run_on_cpu()Chegu Vinod
Introduce an asynchronous version of run_on_cpu() i.e. the caller doesn't have to block till the call back routine finishes execution on the target vcpu. Signed-off-by: Chegu Vinod <chegu_vinod@hp.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2013-07-12Merge remote-tracking branch 'agraf/ppc-for-upstream' into stagingAnthony Liguori
# By Alexander Graf (16) and others # Via Alexander Graf * agraf/ppc-for-upstream: (22 commits) PPC: dbdma: Support more multi-issue DMA requests PPC: Add timer handler for newworld mac-io PPC: dbdma: Support unaligned DMA access PPC: dbdma: Wait for DMA until we have data PPC: dbdma: Move processing to io PPC: dbdma: macio: Add DMA callback PPC: dbdma: Move static bh variable to device struct PPC: dbdma: Introduce kick function PPC: dbdma: Move defines into header file PPC: dbdma: Allow new commands in RUN state PPC: dbdma: Fix debug print PPC: Mac: Add debug prints in macio and dbdma code PPC: dbdma: Replace tabs with spaces PPC: Macio: Replace tabs with spaces PPC: g3beige: Move secondary IDE bus to mac-io PPC: Mac: Fix guest exported tbfreq values target-ppc: Add POWER8 v1.0 CPU model pseries: move interrupt controllers to hw/intc/ spapr: Respect -bios command line option for SLOF spapr: Use named enum for function remove_hpte ... Message-id: 1373562085-29728-1-git-send-email-agraf@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-11PPC: dbdma: Support more multi-issue DMA requestsAlexander Graf
A DMA request can happen for data that hasn't been completely been provided by the IDE core yet. For example - DBDMA request for 0x1000 bytes - IDE request for 1 sector - DBDMA wants to read 0x1000 bytes (8 sectors) from bdrv - breakage Instead, we should truncate our bdrv request to the maximum number of sectors we're allowed to read at that given time. Once that transfer is through, we will fall into our recently introduced waiting logic. - DBDMA requests for 0x1000 bytes - IDE request for 1 sector - DBDMA wants to read MIN(0x1000, 1 * 512) bytes - DBDMA finishes reading, indicates to IDE core that transfer is complete - IDE request for 7 sectors - DBDMA finishes the DMA Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: Add timer handler for newworld mac-ioAlexander Graf
Mac OS X accesses fancy timer registers inside of the mac-io on bootup. These really should be ticking at the mac-io bus frequency, but I don't see anyone upset when we just make them as fast as we want to. With this patch on top of my previous patch queue and latest OpenBIOS I am able to boot Mac OS X 10.4 with -M mac99. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Support unaligned DMA accessAlexander Graf
The DBDMA engine really just reads bytes from a producing device (IDE in our case) and shoves these bytes into memory. It doesn't care whether any alignment takes place or not. Our code today however assumes that block accesses always happen on sector (512 byte) boundaries. This is a fair assumption for most cases. However, Mac OS X really likes to do unaligned, incomplete accesses that it finishes with the next DMA request. So we need to read / write the unaligned bits independent of the actual asynchronous request, because that one can only handle 512-byte-aligned data. We also need to cache these unaligned sectors until the next DMA request, at which point the data might be successfully flushed from the pipe. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Wait for DMA until we have dataAlexander Graf
We should only start processing DMA requests when we have data to process. Hold off working through the DMA shuffling until the IDE core told us that it's ready. This is required because the guest can program the DMA engine or the IDE transfer first. Both are legal. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move processing to ioAlexander Graf
Soon we will introduce intermediate processing pauses which will allow the bottom half to restart a DMA request that couldn't be fulfilled yet. For that to work, move the processing variable into the io struct which is what DMA providers work with. While touching it, also change it into a bool Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: macio: Add DMA callbackAlexander Graf
We need to know when the IDE core starts a DMA transfer. Add a notifier function so we have the chance to start transmitting data. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move static bh variable to device structAlexander Graf
The DBDMA controller has a bottom half to asynchronously process DMA request queues. This bh was stored as a gross static variable. Move it into the device struct instead. While at it, move all users of it to the new generic kick function. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Introduce kick functionAlexander Graf
The DBDMA engine really is running all the time, waiting for input. However we don't want to waste cycles constantly polling. So introduce a kick function that data providers can call to notify the DBDMA controller of new input. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-11PPC: dbdma: Move defines into header fileAlexander Graf
We usually keep struct and constant definitions in header files. Move them there to stay consistent and to make access to fields easier. Signed-off-by: Alexander Graf <agraf@suse.de>
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