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2021-03-06hw/misc/mps2-fpgaio: Make number of LEDs configurable by boardPeter Maydell
The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-6-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-boardPeter Maydell
The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-5-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511Peter Maydell
We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-4-peter.maydell@linaro.org
2021-03-06hw/misc/mps2-scc: Support configurable number of OSCCLK valuesPeter Maydell
Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
2021-03-06hw/arm/mps2-tz: Make SYSCLK frequency board-specificPeter Maydell
The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-2-peter.maydell@linaro.org
2021-03-06hw/display/tcx: Drop unnecessary code for handling BGR format outputsPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel, RGB. The TCX code already assumes 32bpp, but it still has some checks of is_surface_bgr() in an attempt to support 32bpp BGR. is_surface_bgr() will always return false for the qemu_console_surface(), unless the display device itself has deliberately created an alternate-format surface via a function like qemu_create_displaysurface_from(). Drop the never-used BGR-handling code, and assert that we have a 32-bit surface rather than just doing nothing if it isn't. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215102149.20513-1-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Delete unnecessary macroPeter Maydell
The macro draw_line_func is used only once; just expand it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-10-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Inline template header into C filePeter Maydell
We only include the template header once, so just inline it into the source file for the device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-9-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Fix coding style issues in template headerPeter Maydell
Fix some minor coding style issues in the template header, so checkpatch doesn't complain when we move the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-8-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Drop broken bigendian ifdefPeter Maydell
The draw_line16_32() function in the omap_lcdc template header includes an ifdef for the case where HOST_WORDS_BIGENDIAN matches TARGET_WORDS_BIGENDIAN. This is trying to optimise for "source bitmap and destination bitmap format match", but it is broken, because in this function the formats don't match: the source is 16-bit colour and the destination is 32-bit colour, so a memcpy() will produce corrupted graphics output. Drop the bogus ifdef. This bug was introduced in commit ea644cf343129, when we dropped support for DEPTH values other than 32 from the template header. The old #if line was #if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) and this was mistakenly changed to #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN) rather than deleting the #if as now having an always-false condition. Fixes: ea644cf343129 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-7-peter.maydell@linaro.org
2021-03-06hw/display/omap_lcdc: Expand out macros in template headerPeter Maydell
The omap_lcdc template header is already only included once, for DEPTH==32, but it still has all the macro-driven parameterization for other depths. Expand out all the macros in the header. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-6-peter.maydell@linaro.org
2021-03-06hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsitePeter Maydell
The function tc6393xb_draw_graphic32() is called in exactly one place, so just inline the function body at its callsite. This allows us to drop the template header entirely. The code move includes a single added space after 'for' to fix the coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210215103215.4944-5-peter.maydell@linaro.org
2021-03-06hw/display/tc6393xb: Expand out macros in template headerPeter Maydell
Now the template header is included only for BITS==32, expand out all the macros that depended on the BITS setting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-4-peter.maydell@linaro.org
2021-03-05hw/display/tc6393xb: Remove dead code for handling non-32bpp surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the tc6393xb display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-3-peter.maydell@linaro.org
2021-03-05hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfacesPeter Maydell
For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB. Remove the legacy dead code from the milkymist display device which was handling the possibility that the console surface was some other format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215103215.4944-2-peter.maydell@linaro.org
2021-03-05target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé
We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé
IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210221222617.2579610-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne
Section D6.7 of the ARM ARM states: For the purpose of determining Tag Check Fault handling, unprivileged load and store instructions are treated as if executed at EL0 when executed at either: - EL1, when the Effective value of PSTATE.UAO is 0. - EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1} and the Effective value of PSTATE.UAO is 0. ARM has confirmed a defect in the pseudocode function AArch64.TagCheckFault that makes it inconsistent with the above wording. The remedy is to adjust references to PSTATE.EL in that function to instead refer to AArch64.AccessUsesEL(acctype), so that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1. The exception type for synchronous tag check faults remains unchanged. This patch implements the described change by partially reverting commits 50244cc76abc and cc97b0019bb5. Signed-off-by: Peter Collingbourne <pcc@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219201820.2672077-1-pcc@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05virtio-mmio: improve virtio-mmio get_dev_path alogschspa
At the moment the following QEMU command line triggers an assertion failure On xlnx-versal SOC: qemu-system-aarch64 \ -machine xlnx-versal-virt -nographic -smp 2 -m 128 \ -fsdev local,id=shareid,path=${HOME}/work,security_model=none \ -device virtio-9p-device,fsdev=shareid,mount_tag=share \ -fsdev local,id=shareid1,path=${HOME}/Music,security_model=none \ -device virtio-9p-device,fsdev=shareid1,mount_tag=share1 qemu-system-aarch64: ../migration/savevm.c:860: vmstate_register_with_alias_id: Assertion `!se->compat || se->instance_id == 0' failed. This problem was fixed on arm virt platform in commit f58b39d2d5b ("virtio-mmio: format transport base address in BusClass.get_dev_path") It works perfectly on arm virt platform. but there is still there on xlnx-versal SOC. The main difference between arm virt and xlnx-versal is they use different way to create virtio-mmio qdev. on arm virt, it calls sysbus_create_simple("virtio-mmio", base, pic[irq]); which will call sysbus_mmio_map internally and assign base address to subsys device mmio correctly. but xlnx-versal's implements won't do this. However, xlnx-versal can't switch to sysbus_create_simple() to create virtio-mmio device. It's because xlnx-versal's cpu use VersalVirt.soc.fpd.apu.mr as it's memory. which is subregion of system_memory. sysbus_create_simple will add virtio to system_memory, which can't be accessed by cpu. Besides, xlnx-versal can't add sysbus_mmio_map api call too, because this will add memory region to system_memory, and it can't be added to VersalVirt.soc.fpd.apu.mr again. We can solve this by assign correct base address offset on dev_path. This path was test on aarch64 virt & xlnx-versal platform. Signed-off-by: schspa <schspa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()Philippe Mathieu-Daudé
The STATUS register will be reset to IDLE in cnpcm7xx_smbus_enter_reset(), no need to preset it in instance_init(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210228224813.312532-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Speed up aarch64 TBL/TBXRichard Henderson
Always perform one call instead of two for 16-byte operands. Use byte loads/stores directly into the vector register file instead of extractions and deposits to a 64-bit local variable. In order to easily receive pointers into the vector register file, convert the helper to the gvec out-of-line signature. Move the helper into vec_helper.c, where it can make use of H1 and clear_tail. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20210224230532.276878-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' propertyPhilippe Mathieu-Daudé
We hint the 'has_rpu' property is no longer required since commit 6908ec448b4 ("xlnx-zynqmp: Properly support the smp command line option") which was released in QEMU v2.11.0. Beside, this device is marked 'user_creatable = false', so the only thing that could be setting the property is the board code that creates the device. Since the property is not user-facing, we can remove it without going through the deprecation process. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210219144350.1979905-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05tests/qtests: Add npcm7xx emc model testDoug Evans
Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-4-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/arm: Add npcm7xx emc modelDoug Evans
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-3-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05hw/net: Add npcm7xx emc modelDoug Evans
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features. Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-2-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran
Enable FEAT_SSBS for the "max" 32-bit CPU. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-4-rebecca@nuviainc.com [PMM: fix typo causing compilation failure] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Enable FEAT_SSBS for "max" AARCH64 CPURebecca Cran
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-3-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an optional feature in ARMv8.0, and mandatory in ARMv8.5. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210216224543.16142-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05sbsa-ref: add 'max' to list of allowed cpusMarcin Juszkiewicz
Let add 'max' cpu while work goes on adding newer CPU types than Cortex-A72. This allows us to check SVE etc support. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210216150122.3830863-3-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05sbsa-ref: remove cortex-a53 from list of supported cpusMarcin Juszkiewicz
Cortex-A53 supports 40bits of address space. sbsa-ref's memory starts above this limit. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20210216150122.3830863-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging RISC-V PR for 6.0 This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine # gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210304: hw/riscv: virt: Map high mmio for PCIe hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: Drop 'struct MemmapEntry' MAINTAINERS: Add a SiFive machine section goldfish_rtc: re-arm the alarm after migration docs/system: riscv: Add documentation for sifive_u machine docs/system: Add RISC-V documentation docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/ssi: Add SiFive SPI controller support hw/block: m25p80: Add various ISSI flash information hw/block: m25p80: Add ISSI SPI flash support target-riscv: support QMP dump-guest-memory roms/opensbi: Upgrade from v0.8 to v0.9 hw/misc: sifive_u_otp: Use error_report() when block operation fails target/riscv: Declare csr_ops[] with a known size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng
Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng
RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng
`link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04MAINTAINERS: Add a SiFive machine sectionAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bin.meng@windriver.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 6bc077e5ae4a9512c8adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com
2021-03-04goldfish_rtc: re-arm the alarm after migrationLaurent Vivier
After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201220112615.933036-7-laurent@vivier.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: riscv: Add documentation for sifive_u machineBin Meng
This adds detailed documentation for RISC-V `sifive_u` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Machine-specific options - Running Linux kernel - Running VxWorks kernel - Running U-Boot, and with an alternate configuration Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 20210126060007.12904-10-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: Add RISC-V documentationBin Meng
Add RISC-V system emulator documentation for generic information. `Board-specific documentation` and `RISC-V CPU features` are only a placeholder and will be added in the future. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-9-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: Sort targets in alphabetical orderBin Meng
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-8-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng
All other peripherals' IRQs are in the format of decimal value. Change SIFIVE_U_GEM_IRQ to be consistent. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the <reg> property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add various ISSI flash informationBin Meng
This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add ISSI SPI flash supportBin Meng
This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang
Add the support needed for creating prstatus elf notes. This allows us to use QMP dump-guest-memory. Now ELF notes of RISC-V only contain prstatus elf notes. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 20210201124458.1248-2-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04roms/opensbi: Upgrade from v0.8 to v0.9Bin Meng
Upgrade OpenSBI from v0.8 to v0.9 and the pre-built bios images. The v0.9 release includes the following commits: 35bc810 docs/platform: Update QEMU parameter for fw_payload 78afe11 config.mk: Update QEMU run command for generic and sifive fu540 platforms ec3e5b1 docs/platform: sifive_fu540: Update U-Boot instructions 7d61a68 README.md: fix markdown link formatting a5f9104 lib/utils: fdt: Update FDT expand size to 1024 for reserved memory node ec1abf6 include: sbi_bitops: Remove dead shift assignment in ffs/fls 8e47649 lib: Add sbi_strncmp implementation 2845d2d lib: utils: Add a macro in libfdt_env.h for strncmp 2cfd2fc lib: utils: Use strncmp in fdt_parse_hart_id() 937caee lib: sbi_misaligned_ldst: Determine transformed instruction length correctly 4b18a2a firmware: fw_base: Improve exception stack setup in trap handler 9d56961 lib: sbi_trap: Fix hstatus.SPVP update in sbi_trap_redirect() d7f87d9 platform: kendryte/k210: fixup FDT e435ba0 lib: sbi_init: Avoid thundering hurd problem with coldboot_lock 4f3bad6 lib: sbi: Handle the case where MTVAL has illegal instruction address 7b0b289 lib: sbi: Remove redundant SBI_HART_HAS_PMP feature 74d1db7 lib: sbi: Improve PMP CSR detection and progamming 2c341f7 lib: sbi: Detect and print MHPM counters at boot-time 162d453 include: sbi: Few cosmetic changes in riscv_encoding.h ebc8ebc lib: sbi: Improve HPM CSR read/write emulation dcb10c0 lib: sbi: Don't handle VS-mode ecall in sbi_trap_handler() bef63d6 include: Rename ECALL defines to match latest RISC-V spec c1c7c3e lib: sbi_trap: Allow M-mode to M-mode ECALLs 6734304 lib: sbi: Allow specifying start mode to sbi_hsm_hart_start() API 7ccf6bf lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API 9f935a4 lib: utils: Improve fdt_cpu_fixup() implementation 172fa16 lib: sbi: Ensure coldboot HART supports next privilege mode aaeca7e platform: generic: Don't mark non-MMU HARTs as invalid 7701ea1 lib: sbi: Fix PMP CSR detection 79bf80b lib: sbi_scratch: typo scatch a04c465 makefile: fix clean directive af4b50f Makefile: Build ELF, BIN and LD script in platform build directory 6ca0969 firmware: Add common FW_FDT_PATH compile-time option 9c07c51 firmware: Remove FW_PAYLOAD_FDT_PATH compile-time option e9a4bfb Makefile: Allow padding zeros when converting DTB to C source a0f2d4a platform: kendryte/k210: Add some padding for FDT fixups dbeeacb include: sbi: Remove redundant includes from sbi_platform.h a12d46a include: sbi: Remove pmp_region callbacks from sbi_platform_operations a126886 lib: sbi: Configure PMP late in coldboot and warmboot path f81d6f6 lib: sbi: Remove redundant hartid parameter from sbi_hart_init() 8b65005 include: sbi: Make hartmask pointer const in sbi_hartmask_test_hart() b1678af lib: sbi: Add initial domain support e73b92d lib: sbi: Extend sbi_hsm_hart_started_mask() for domains 3a30d2c lib: sbi: Extend sbi_hsm_hart_start() for domains 530e95b lib: sbi: Optimize sbi_hsm_hart_started_mask() implementation 3e20037 lib: sbi: Extend sbi_system_reset() for domains 5edbb7c lib: utils: Update fdt_reserved_memory_fixup() to use current domain 5fd99db lib: utils: Update fdt_cpu_fixup() to use current domain e856462 lib: sbi: Remove redundant sbi_hart_pmp_xyz() functions c10c30b lib: sbi: Configure PMP based on domain memory regions c347408 lib: sbi: Display domain details in boot prints fdf5d5c docs: Add initial documentation for domain support 74c0ea1 lib: utils: Implement "ranges" property parsing bf21632 lib: sbi: Detect PMP granularity and number of address bits a809f40 lib: sbi: Improve boot time print with additional PMP information 914f81f Makefile: Add option to use toolchain default ABI and ISA string 48616b3 lib: sbi: Improve boot prints in cold boot sequence 781cafd docs: fix a typo error 54a7734 include: sbi: Add SBI SRST extension related defines c4acc60 include: sbi: Remove opensbi specific reset type defines da07479 platform: Remove dummy system reset functions 5c429ae lib: sbi: Improve system reset platform operations 548d03e lib: sbi: Implement System Reset (SRST) SBI extension 2677324 firmware: fw_base: Optimize trap handler for RV32 systems 8d2edc4 lib: sbi: Fix sbi_hart_switch_mode() for u-mode 3d921fa lib: sbi: Fix typo in sbi_domain_finalize() 4e37022 lib: sbi: Fix domain_count check in sbi_domain_finalize() c709d40 lib: sbi: Auto start domain only if boot HART within limits c1f6d89 include: sbi: Use lower bits for domain memory region permissions 62ea4f4 lib: sbi: Override domain boot HART when coldboot HART assigned to it 555e737 lib: sbi: Add error prints in sbi_domain_finalize() 9b65dca include: sbi: Add domains_init() platform operation c0d2baa docs: Add domain device tree binding documentation ba741ea lib: utils: Add helper routines to populate domains from FDT 4fffb53 platform: generic: Populate domains from FDT e7da0b4 lib: utils/libfdt: Upgrade to v1.6.0 release 2179777 lib: utils: Allow FDT domain iteration functions to fail 7baccfc lib: sbi: Add function to register new domain 6fc1986 lib: utils: Remove fdt_domain_get() function a029bd9 lib: sbi: Remove domain_get() platform callback function 7dcb1e1 lib: sbi: Fix sign-extension in sbi_misaligned_load_handler() 80bc506 lib: sbi: Replace args with trap registers in ecall handler b7df5e4 lib: sbi: Introduce sbi_trap_exit() API 12394a2 lib: sbi: Allow custom local TLB flush function 0d49c3b lib: utils: Fix shakti uart implementation db56341 lib: sbi: Allow platforms to provide root domain memory regions e884416 include: sbi: No need to pack struct sbi_trap_regs 386eba2 include: sbi: No need to pack struct sbi_scratch 1bbf361 include: sbi: Don't pack struct sbi_platform and sbi_platform_operations da5293f platform: template: Fix compile error 234ed8e include: Bump-up version to 0.9 Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: 20210119234438.10132-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/misc: sifive_u_otp: Use error_report() when block operation failsBin Meng
At present when blk_pread() / blk_pwrite() fails, a guest error is logged, but this is not really a guest error. Change to use error_report() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611026585-29971-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng
csr_ops[] is currently declared with an unknown size in cpu.h. Since the array size is known, let's do a complete declaration. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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