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AgeCommit message (Expand)Author
2023-02-07hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registersPhilippe Mathieu-Daudé
2023-02-07hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'Philippe Mathieu-Daudé
2023-02-07hw/nvram/eeprom_at24c: Make reset behavior more like hardwarePeter Delevoryas
2023-02-07hw/arm/aspeed: Add aspeed_eeprom.cPeter Delevoryas
2023-02-07hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helperPeter Delevoryas
2023-02-07hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_initPeter Delevoryas
2023-02-07hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boardsPeter Delevoryas
2023-02-07hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mrCédric Le Goater
2023-02-07tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK bootCédric Le Goater
2023-02-07tests/avocado/machine_aspeed.py: update buildroot testsCédric Le Goater
2023-02-07m25p80: Add the is25wp256 SFPD tableGuenter Roeck
2023-02-07avocado/boot_linux_console.py: Update ast2600 testJoel Stanley
2023-02-07hw/net: Fix read of uninitialized memory in ftgmac100Stephen Longfield
2023-02-07aspeed: Add Supermicro X11 SPI machine typeGuenter Roeck
2023-02-07tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiBPhilippe Mathieu-Daudé
2023-02-07tests/avocado: Introduce file_truncate()Philippe Mathieu-Daudé
2023-02-07hw/riscv: virt: Simplify virt_{get,set}_aclint()Bin Meng
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta
2023-02-07target/riscv: add a MAINTAINERS entry for XThead* extension supportChristoph Müllner
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07hw/riscv: change riscv_compute_fdt_addr() semanticsDaniel Henrique Barboza
2023-02-07hw/riscv: split fdt address calculation from fdt loadDaniel Henrique Barboza
2023-02-07hw/riscv/boot.c: calculate fdt size after fdt_pack()Daniel Henrique Barboza
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'Daniel Henrique Barboza
2023-02-07hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'Daniel Henrique Barboza
2023-02-07hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()Daniel Henrique Barboza
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-02-07hw/riscv: boot: Don't use CSRs if they are disabledAlistair Francis
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich
2023-02-06migration: save/delete migration thread infoJiang Jiacheng
2023-02-06migration: Introduce interface query-migrationthreadsJiang Jiacheng