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2019-06-27disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan
The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-27disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark
Due to the design of the disassembler, the immediate is not known during decoding of the opcode; so to handle compressed encodings with reserved immediate values (non-zero), we need to add an additional check during decompression to match reserved encodings with zero immediates and translate them into the illegal instruction. The following compressed opcodes have reserved encodings with zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli, c.srai, c.andi and c.slli Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Broke long lines] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-26MAINTAINERS: Change maintership of Xen code under hw/9pfsGreg Kurz
Xen folks are the actual maintainers for this. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Paul Durrant <paul.durrant@citrix.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Message-Id: <155912548463.2019004.3515830305299809902.stgit@bahia.lan> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26configure: use valid args testing sem_timedwaitDaniel P. Berrangé
The sem_timedwait function has been annotated as requiring non-null args in latest header files from GCC snapshot representing the future 2.30 release. This causes configure to fail when -Werror is used: config-temp/qemu-conf.c: In function ‘main’: config-temp/qemu-conf.c:2:25: error: null argument where non-null required (argument 1) [-Werror=nonnull] 2 | int main(void) { return sem_timedwait(0, 0); } | ^~~~~~~~~~~~~ config-temp/qemu-conf.c:2:25: error: null argument where non-null required (argument 2) [-Werror=nonnull] Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190617114114.24897-1-berrange@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26configure: disallow spaces and colons in source path and build pathAntonio Ospite
The configure script breaks when the qemu source directory is in a path containing white spaces, in particular the list of targets is not correctly generated when calling "./configure --help" because of how the default_target_list variable is built. In addition to that, *building* qemu from a directory with spaces breaks some assumptions in the Makefiles, even if the original source path does not contain spaces like in the case of an out-of-tree build, or when symlinks are involved. To avoid these issues, refuse to run the configure script and the Makefile if there are spaces or colons in the source path or the build path, taking as inspiration what the kbuild system in linux does. Buglink: https://bugs.launchpad.net/qemu/+bug/1817345 Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Antonio Ospite <antonio.ospite@collabora.com> Message-Id: <20190526144747.30019-3-ao2@ao2.it> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26configure: set source_path only once and make its definition more robustAntonio Ospite
Since commit 79d77bcd36 (configure: Remove --source-path option, 2019-04-29) source_path cannot be overridden anymore, move it out of the "default parameters" block since the word "default" may suggest that the value can change, while in fact it does not. While at it, only set source_path once and separate the positional argument of basename with "--" to more robustly cover the case of path names starting with a dash. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Antonio Ospite <antonio.ospite@collabora.com> Message-Id: <20190526144747.30019-2-ao2@ao2.it> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26linux-user/m68k: remove simulator syscall interfaceLaurent Vivier
This interface has been introduced in 2005 with the coldfire implementation (e6e5906b6e ColdFire target.) and looks like to do what the linux-user interface already does with the TRAP exception rather than the ILLEGAL exception. This interface has not been maintained since that. The semi-hosting interface is not removed so coldfire kernel with semi-hosting is always supported. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190524162049.806-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26m68k comments break patch submission due to being incorrectly formattedLucien Murray-Pitts
Altering all comments in target/m68k to match Qemu coding styles so that future patches wont fail due to style breaches. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190606234125.GA4830@localhost.localdomain> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26The m68k gdbstub SR reg request doesnt include Condition-CodesLucien Murray-Pitts
The register request via gdbstub would return the SR part which contains the Trace/Master/IRQ state flags, but would be missing the CR (Condition Register) state bits. This fix adds this support by merging them in the m68k specific gdbstub handler m68k_cpu_gdb_read_register for SR register. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190609105154.GA16755@localhost.localdomain> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26target/mips: Fix big endian host behavior for interleave MSA instructionsAleksandar Markovic
Fix big endian host behavior for interleave MSA instructions. Previous fix used TARGET_WORDS_BIGENDIAN instead of HOST_WORDS_BIGENDIAN, which was a mistake. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Fix some test cases for pack MSA instructionsAleksandar Markovic
Fix certian test cases for MSA pack instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Add support for MSA MIPS32R6 testingsAleksandar Markovic
Add files for MSA MIPS32R6 target testings (copiling and running). Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Add support for MSA big-endian target testingsAleksandar Markovic
Add files for MSA big-endian target testings (copiling and running). Little-endian files are renamed and ammended too. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Amend tests for MSA int multiply instructionsAleksandar Markovic
Amend tests for MSA int multiply instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Amend tests for MSA int dot product instructionsAleksandar Markovic
Add tests for instructions whose result depends on the value in destination register (prior to instruction execution). Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Add tests for MSA move instructionsAleksandar Markovic
Add tests for MSA move instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26tests/tcg: target/mips: Add tests for MSA bit move instructionsAleksandar Markovic
Add tests for MSA bit move instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26dma/rc4030: Minor code style cleanupAleksandar Markovic
Fix some simple checkpatch.pl warnings in rc4030.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561472838-32272-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26dma/rc4030: Fix off-by-one error in specified memory region sizeAleksandar Markovic
The size is one byte less than it should be: address-space: rc4030-dma 0000000000000000-00000000fffffffe (prio 0, i/o): rc4030.dma rc4030 is used in MIPS Jazz board context. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561472838-32272-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26hw/mips/gt64xxx_pci: Align the pci0-mem sizePhilippe Mathieu-Daudé
One byte is missing, use an aligned size. (qemu) info mtree memory-region: pci0-mem 0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem ^ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-8-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Convert debug printf()s to trace eventsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-7-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-6-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Fix 'spaces' coding style issuesPhilippe Mathieu-Daudé
Since we'll move this code around, fix its style first: ERROR: space prohibited between function name and open parenthesis ERROR: line over 90 characters Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-5-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Fix 'braces' coding style issuesPhilippe Mathieu-Daudé
Since we'll move this code around, fix its style first: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-4-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Fix 'tabs' coding style issuesPhilippe Mathieu-Daudé
Since we'll move this code around, fix its style first: ERROR: code indent should never use tabs Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-3-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Fix multiline comment syntaxPhilippe Mathieu-Daudé
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-2-f4bug@amsat.org>
2019-06-25riscv: virt: Add cpu-topology DT node.Atish Patra
Currently, there is no cpu topology defined in RISC-V. Define a device tree node that clearly describes the entire topology. This saves the trouble of scanning individual cache to figure out the topology. Here is the linux kernel patch series that enables topology for RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html CPU topology after applying this patch in QEMU & above series in kernel / # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list 2 / # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id 0 / # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25RISC-V: Update syscall list for 32-bit support.Jim Wilson
32-bit RISC-V uses _llseek instead of lseek as syscall number 62. Update syscall list from open-embedded build, primarily because 32-bit RISC-V requires statx support. Tested with cross gcc testsuite runs for rv32 and rv64, with the pending statx patch also applied. Signed-off-by: Jim Wilson <jimw@sifive.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing <joel@sing.id.au> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-06-25tricore: add QSEED instructionAndreas Konopik
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20190624070339.4408-6-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [BK: Added fp_status arg to float32_is_signaling_nan()]
2019-06-25tricore: sync ctx.hflags with tb->flagsGeorg Hofstetter
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20190624070339.4408-5-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-06-25tricore: fix RRPW_INSERT instructionDavid Brenken
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20190624070339.4408-4-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-06-25tricore: add UTOF instructionDavid Brenken
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20190624070339.4408-3-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-06-25tricore: add FTOIZ instructionDavid Brenken
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de> Signed-off-by: David Brenken <david.brenken@efs-auto.de> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20190624070339.4408-2-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
Add support for disabling/enabling the "Counters" extension. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Remove user version informationAlistair Francis
Remove the user version information. This was never used and never publically exposed in a release of QEMU, so let's just remove it. In future to manage versions we can extend the extension properties to specify version. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new 1.10.0 and the ratified 1.11.0. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis
1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1 but has different semantics. This patch enables the CSR for 1.11-based targets, which is trivial to implement because the counters in QEMU never tick (legal according to the spec). Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-24linux-user: set default PPC64 CPULaurent Vivier
The default CPU for pseries has been set to POWER9 by default. We can use the same default for linux-user Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190609143521.19374-2-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24linux-user: update PPC64 HWCAP2 feature listLaurent Vivier
QEMU_PPC_FEATURE2_VEC_CRYPTO enables the use of VSX instructions in libcrypto that are accelerated by the TCG vector instructions now. QEMU_PPC_FEATURE2_DARN allows to use the new builtin qemu_guest_getrandom() function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190609143521.19374-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24linux-user: Add support for setsockopt() options IPV6_<ADD|DROP>_MEMBERSHIPNeng Chen
Add support for the option IPV6_<ADD|DROP>_MEMBERSHIP of the syscall setsockopt(). This option controls membership in multicast groups. Argument is a pointer to a struct ipv6_mreq. The glibc <netinet/in.h> header defines the ipv6_mreq structure, which includes the following members: struct in6_addr ipv6mr_multiaddr; unsigned int ipv6mr_interface; Whereas the kernel in its <linux/in6.h> header defines following members of the same structure: struct in6_addr ipv6mr_multiaddr; int ipv6mr_ifindex; POSIX defines ipv6mr_interface [1]. __UAPI_DEF_IVP6_MREQ appears in kernel headers with v3.12: cfd280c91253 net: sync some IP headers with glibc Without __UAPI_DEF_IVP6_MREQ, kernel defines ipv6mr_ifindex, and this is explained in cfd280c91253: "If you include the kernel headers first you get those, and if you include the glibc headers first you get those, and the following patch arranges a coordination and synchronization between the two." So before 3.12, a program can't include both <netinet/in.h> and <linux/in6.h>. In linux-user/syscall.c, we only include <netinet/in.h> (glibc) and not <linux/in6.h> (kernel headers), so ipv6mr_interface is the one to use. [1] http://pubs.opengroup.org/onlinepubs/009695399/basedefs/netinet/in.h.html Signed-off-by: Neng Chen <nchen@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1560953834-29584-2-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24linux-user: Add support for setsockopt() option SOL_ALGYunqiang Su
Add support for options SOL_ALG of the syscall setsockopt(). This option is used in relation to Linux kernel Crypto API, and allows a user to set additional information for the cipher operation via syscall setsockopt(). The field "optname" must be one of the following: - ALG_SET_KEY – seting the key - ALG_SET_AEAD_AUTHSIZE – set the authentication tag size SOL_ALG is relatively newer setsockopt() option. Therefore, the code that handles SOL_ALG is enclosed in "ifdef" so that the build does not fail for older kernels that do not contain support for SOL_ALG. "ifdef" also contains check if ALG_SET_KEY and ALG_SET_AEAD_AUTHSIZE are defined. Signed-off-by: Yunqiang Su <ysu@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1560953834-29584-3-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24linux-user: emulate msgsnd(), msgrcv() and semtimedop()Laurent Vivier
When we have updated kernel headers to 5.2-rc1 we have introduced new syscall numbers that can be not supported by older kernels and fail with ENOSYS while the guest emulation succeeded before because the syscalls were emulated with ipc(). This patch fixes the problem by using ipc() if the new syscall returns ENOSYS. Fixes: 86e636951ddc ("linux-user: fix __NR_semtimedop undeclared error") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20190529084804.25950-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24util/path: Do not cache all filenames at startupRichard Henderson
If one uses -L $PATH to point to a full chroot, the startup time is significant. In addition, the existing probing algorithm fails to handle symlink loops. Instead, probe individual paths on demand. Cache both positive and negative results within $PATH, so that any one filename is probed only once. Use glib filename functions for clarity. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190519201953.20161-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-24Merge tag 's390x-tcg-2019-06-21' into s390-next-stagingCornelia Huck
One fix for a tcg test case and two cleanups/refactorings of cpu feature definitions. # gpg: Signature made Fri 21 Jun 2019 03:37:37 PM CEST # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-06-21': s390x/cpumodel: Prepend KDSA features with "KDSA" s390x/cpumodel: Rework CPU feature definition tests/tcg/s390x: Fix alignment of csst parameter list Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-24vfio-ccw: support async command subregionCornelia Huck
A vfio-ccw device may provide an async command subregion for issuing halt/clear subchannel requests. If it is present, use it for sending halt/clear request to the device; if not, fall back to emulation (as done today). Reviewed-by: Farhan Ali <alifm@linux.ibm.com> Message-Id: <20190613092542.2834-1-cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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