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2011-01-18mips: Break out cpu_mips_timer_expireEdgar E. Iglesias
Reorganize for future patches, no functional change. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-17Replace 'extern inline' with 'static inline'Blue Swirl
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-17bsd-user: Fix possible memory leaks and wrong realloc callStefan Weil
These errors were reported by cppcheck: [bsd-user/elfload.c:1108]: (error) Common realloc mistake: "syms" nulled but not freed upon failure [bsd-user/elfload.c:1076]: (error) Memory leak: s [bsd-user/elfload.c:1079]: (error) Memory leak: syms v2: * The previous fix for memory leaks was incomplete (thanks to Peter Maydell for te hint). * Fix wrong realloc usage, too. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-17sm501: add 2D engine copyrect supportAurelien Jarno
Linux kernel started to use the SM501 2D engine for the console, and especially the copyrect operation. Implement this operation so that recent kernels can be used with QEMU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-17Merge remote branch 'mst/for_anthony' into stagingAnthony Liguori
2011-01-16m48t59: Fix a wrong opaque passed to nvram read and write routinesHervé Poussineau
This fixes boot on PPC prep. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16gdbstub: Close connection in gdb_exitFabien Chouteau
On Windows, this is required to flush the remaining data in the IO stream, otherwise Gdb do not receive the last packet. Version 2: Fix linux-user build error. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
2011-01-16USB keyboard emulation key mapping errorMichael Tokarev
The USB keyboard emulation's translation table in hw/usb-hid.c doesn't match the codes actually sent for the Logo (a.k.a. "Windows") or Menu keys. This results in the guest OS not being able to receive these keys at all when the USB keyboard emulation is being used. In particular, both the keymap in /usr/share/kvm/keymaps/modifiers and the evdev table in x_keymap.c map these keys to 0xdb, 0xdc, and 0xdd, while usb_hid_usage_keys[] seems to be expecting them to be mapped to 0x7d, 0x7e, and 0x7f. The attached patch seems to fix the problem, at least in my (limited) testing. http://bugs.debian.org/578846 http://bugs.debian.org/600593 (cloned from the above against different pkg) https://bugs.launchpad.net/qemu/+bug/584139 Signed-Off-By: Brad Jorsch <anomie@users.sourceforge.net> Signed-Off-By: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16target-sh4: implement negc using TCGAurelien Jarno
Using setcond it's now possible to generate a relatively short negc instruction in TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16target-sh4: use rotl/rotr when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16tcg/sparc64: fix segfaultBlue Swirl
With current OpenBSD, code_gen_buffer was mapped 8GB away from text segment. Then any helpers were beyond the 2GB range of call instruction genereated by TCG and so the calls would go nowhere, leading to a segfault. Fix by specifying an address for the code_gen_buffer, hopefully free and nearby the helpers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-15target-sh4: correct use of ! and &Aurelien Jarno
Fix wrong usage of ! and & in MMU related functions. Thanks to Blue Swirl for reporting the issue. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-15monitor: fix a typoBlue Swirl
Fix usage of wrong variable, spotted by clang: /src/qemu/monitor.c:2278:36: warning: The left operand of '&' is a garbage value prot = pde & (PG_USER_MASK | PG_RW_MASK | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-14make_device_config: Fix non-fatal error message with dash and other shellsStefan Weil
ORS=" " adds a blank to the name of the include file. Some shells (e.g. dash) don't accept input redirection (tr -d '\r' < $f) when $f ends with a blank, so they print an error message instead of reading pci.mak. This is a non-fatal error because pci.mak does not contain an include line. It was introduced by commit 5d6b423c5cd6f9dfac30959ff1d5c088996719c3. Using printf avoids adding a blank and is also supported by older awk versions (this solution was suggested by Paolo Bonzini, thank you). Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Tested-by: Andreas Färber <andreas.faerber@web.de>
2011-01-14MAINTAINERS: add entries for TCGAurelien Jarno
The MAINTAINERS file was lacking entries concerning the TCG code, add them based on the git history. For the common TCG code, is probably better to keep qemu-devel@non-gnu.org as this code can break easily, so it's better to get it reviewed by a few persons. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14MAINTAINERS: Change MIPS and SH4 maintainersAurelien Jarno
Since nobody else seems interested in maintaining MIPS and SH4 targets, and as I have done most of the recent code changes, let officialize that. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14MAINTAINERS: fix typosAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Restore IT bits when resuming after an exceptionPeter Maydell
We were not correctly restoring the IT bits when resuming execution after taking an unexpected exception in the middle of an IT block. Fix this by tracking them along with PC changes and restoring in gen_pc_load(). This fixes bug https://bugs.launchpad.net/qemu/+bug/581335 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14linux-user: ARM: clear the IT bits when invoking a signal handlerPeter Maydell
When invoking a signal handler for an ARM target, make sure the IT bits in the CPSR are cleared. (This would otherwise cause incorrect execution if the IT state was non-zero when an exception occured. This bug has been masked previously because we weren't getting the IT state bits at exception entry right anyway.) Also use the proper cpsr_read()/cpsr_write() interface to update the CPSR rather than manipulating CPUState fields directly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Refactor translation of exception generating instructionsPeter Maydell
Create a new function which does the common sequence of gen_set_condexec, gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Remove redundant setting of IT bits before Thumb SWIPeter Maydell
Remove a redundant call to gen_set_condexec() in the translation of Thumb mode SWI. (SWI and WFI generate "exceptions" which happen after the execution of the instruction, ie when PC and IT bits have updated. So the condexec bits at this point are not correct. However, the code that handles finishing the translation of the TB will write the correct value of the condexec bits later, so the only effect was that a conditional Thumb SWI would generate slightly worse code than necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with user-state from TB flags, not CPUStatePeter Maydell
When translating, get the user/priv state from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Set privileged bit in TB flags correctly for M profilePeter Maydell
M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with condexec bits from TB flags, not CPUStatePeter Maydell
When translating, the condexec bits for the TB are in the TB flags; the CPUState condexec bits may be different. This patch fixes https://bugs.launchpad.net/bugs/604872 where we might segfault if we took an exception in the middle of a TB with an IT block, because when we came to retranslate in cpu_restore_state() the CPUState condexec bits would have advanced compared to the start of the TB and we would generate different (wrong) code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with Thumb state from TB flags, not CPUStatePeter Maydell
The Thumb/ARM state for the TB being translated should come from the TB flags, not the CPUState. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP len/stride from TB flags, not CPUStatePeter Maydell
When translating, the VFP vector length and stride for this TB are encoded in the TB flags; the CPUState copies may be different and must not be used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Translate with VFP-enabled from TB flags, not CPUStatePeter Maydell
When translating code, whether the VFP unit is enabled for this TB is stored in a bit in the TB flags. Use this rather than incorrectly reading the FPEXC from the CPUState passed to translation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Add symbolic constants for bitfields in TB flagsPeter Maydell
Add symbolic constants for the bitfields we use in the TB flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Don't generate code specific to current CPU mode for SRSPeter Maydell
When translating the SRS instruction, handle the "store registers to stack of current mode" case in the helper function rather than inline. This means the generated code does not make assumptions about the current CPU mode which might not be valid when the TB is executed later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Use the standard FPSCR value for VRSQRTSPeter Maydell
VSQRTS always uses the standard FPSCR value as it is a Neon instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Add support for 'Standard FPSCR Value' as used by NeonPeter Maydell
Add support to the ARM helper routines for a second fp_status value which should be used for operations which the ARM ARM indicates use "ARM standard floating-point arithmetic" rather than being controlled by the rounding/flush/NaN settings in the FPSCR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Fix implementation of VRSQRTSPeter Maydell
The implementation of the ARM VRSQRTS instruction (which calculates (3 - op1 * op2) / 2) was missing the division operation. It also did not handle the special cases of (0,inf) and (inf,0). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14softfloat: Add float32_is_zero_or_denormal() functionPeter Maydell
Add a utility function to softfloat to test whether a float32 is zero or denormal. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14lsi53c895a: fix endianness issuesAurelien Jarno
lsi_ram_read*() and lsi_ram_write*() are not consistent, one uses leXX_to_cpu() the other uses nothing. As the comment above the RAM declaration says: "Script ram is stored as 32-bit words in host byteorder.", remove the leXX_to_cpu() calls. This fixes the boot of an ARM versatile machine on MIPS and PowerPC hosts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14mips/malta: fix board idAurelien Jarno
Board id can't be written with stl_phys() as it's read-only part of memory. Use stl_p() on the memory buffer instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: use setcond when possibleAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: log instructions start in TCG codeAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: simplify comparisons after a 'and' opAurelien Jarno
When a TCG variable is anded with a value and the compared with the same value, we can simply invert the comparison and compare it with 0. The generated code is smaller. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: fix reset on r2dAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: optimize exceptionsAurelien Jarno
As exception is not the normal path, don't bother saving PC, before raising one, instead rely on code retranslation to get the CPU state. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add ftrv instructionAurelien Jarno
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add fipr instructionAurelien Jarno
Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: implement FPU exceptionsAurelien Jarno
FPU exception support where not implemented on SH4. Implement them by clearing the softfloat exceptions flags before an FP instruction (the SH4 FPU also clear them before an instruction), and calling a function to update the FPSCR register after an FP instruction. This function update the corresponding FPSCR bits (both flags and cumulative flags) and trigger exception if enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: implement flush-to-zeroAurelien Jarno
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as zero. Enable the corresponding softfloat option when this bit is set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: define FPSCR constantsAurelien Jarno
Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: use default-NaN modeAurelien Jarno
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones. Enable the default-NaN mode by default. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14softfloat: fix default-NaN modeAurelien Jarno
When the default-NaN mode is enabled, it should return the default NaN value, but it should anyway raise the invalid operation flag if one of the operand is an sNaN. I have checked that this behavior matches the ARM and SH4 manuals, as well as real SH4 hardware. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14softfloat: SH4 has the sNaN bit setAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: switch sh4 to softfloatAurelien Jarno
We need to be able to catch exceptions correctly and thus enable softfloat on SH4. As all machines except i386 and x86_64 are using softfloat, make it the default and change the case to detect i386 and x86_64. Note that CRIS doesn't have an FPU, so it can be configured with both softfloat-native and softfloat. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14configure: fix broken testAurelien Jarno
Since commit d1807a4f836c27f6dc7061e53a834dd27f78e46a ./configure tries to test files and directories with "test -f", which only test for regular files. Test with "test -e", which looks for any kind of files. This unbreak the configure script when not using a separate object directory. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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