aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2011-04-01ccid: add passthru card deviceAlon Levy
The passthru ccid card is a device sitting on the usb-ccid bus and using a chardevice to communicate with a remote device using the VSCard protocol defined in libcacard/vscard_common.h Usage docs available in following patch in docs/ccid.txt Signed-off-by: Alon Levy <alevy@redhat.com> --- Changes from v23->v24: * fixed double license line in header. Changes from v20->v21: (Jes Sorensen review) * add reference to COPYING in header * long comment reformatting Changes from v19->v20: * checkpatch.pl Changes from v18->v19: * add qdev.desc * remove .qdev.unplug (no hot unplug support for ccid bus) Changes from v16->v17: * fix wrong cast when receiving VSC_Error * ccid-card-passthru: force chardev user wakeup by sending Init see lengthy comment below. Changes from v15->v16: Behavioral changes: * return correct size * return error instead of assert if client sent too large ATR * don't assert if client sent too large a size, but add asserts for indices to buffer * reset vscard_in indices on chardev disconnect * handle init from client * error if no chardev supplied * use ntoh, hton * eradicate reader_id_t * remove Reconnect usage (removed from VSCARD protocol) * send VSC_SUCCESS on card insert/remove and reader add/remove Style fixes: * width of line fix * update copyright * remove old TODO's * update file header comment * use macros for debug levels * c++ style comment replacement * update copyright license * fix ATR size comment * fix whitespace in struct def * fix DPRINTF prefix * line width fix ccid-card-passthru: force chardev user wakeup by sending Init The problem: how to wakeup the user of the smartcard when the smartcard device is initialized? Long term solution: have a callback interface. This was done via the deprecated so called chardev ioctl interface. Short term solution: do a write. Specifically we write an Init message. And we change the client to send it's own Init message regardless of receiving this one. Additional Init messages will be regarded as acceptable, the first one received after connection establishment is the determining one wrt capabilities.
2011-04-01introduce libcacard/vscard_common.hAlon Levy
--- Signed-off-by: Alon Levy <alevy@redhat.com> v20->v21 changes: (Jes Sorensen review) * license set to 2+ * long comment fixes, remove empty line at eof. * add reference to COPYING v19->v20 changes: * checkpatch.pl v15->v16 changes: Protocol change: * VSCMsgInit capabilities and magic * removed ReaderResponse, will use Error instead with code==VSC_SUCCESS. * adaded Flush and FlushComplete, remove Reconnect. * define VSCARD_MAGIC * added error code VSC_SUCCESS. Fixes: * update VSCMsgInit comment * fix message type enum * remove underscore from wrapping define * update copyright * updated comments. * Header comment updated * remove C++ style comment * fix comment for VSCMsgError * give names to enums in typedefs
2011-04-01usb-ccid: add CCID busAlon Levy
A CCID device is a smart card reader. It is a USB device, defined at [1]. This patch introduces the usb-ccid device that is a ccid bus. Next patches will introduce two card types to use it, a passthru card and an emulated card. [1] http://www.usb.org/developers/devclass_docs/DWG_Smart-Card_CCID_Rev110. Signed-off-by: Alon Levy <alevy@redhat.com> --- changes from v20->v21: (Jes Sorenson review) * cosmetic changes - fix multi line comments. * reorder fields in USBCCIDState * add reference to COPYING * add --enable-smartcard and --disable-smartcard here (moved from last patch) changes from v19->v20: * checkpatch.pl changes from v18->v19: * merged: ccid.h: add copyright, fix define and remove non C89 comments * add qdev.desc changes from v15->v16: Behavioral changes: * fix abort on client answer after card remove * enable migration * remove side affect code from asserts * return consistent self-powered state * mask out reserved bits in ccid_set_parameters * add missing abRFU in SetParameters (no affect on linux guest) whitefixes / comments / consts defines: * remove stale comment * remove ccid_print_pending_answers if no DEBUG_CCID * replace printf's with DPRINTF, remove DEBUG_CCID, add verbosity defines * use error_report * update copyright (most of the code is not original) * reword known bug comment * add missing closing quote in comment * add missing whitespace on one line * s/CCID_SetParameter/CCID_SetParameters/ * add comments * use define for max packet size Comment for "return consistent self-powered state": the Configuration Descriptor bmAttributes claims we are self powered, but we were returning not self powered to USB_REQ_GET_STATUS control message. In practice, this message is not sent by a linux 2.6.35.10-74.fc14.x86_64 guest (not tested on other guests), unless you issue lsusb -v as root (for example).
2011-04-01qemu-thread.h: include inttypes.hAlon Levy
qemu-thread.h relies on uint64_t being defined, but doesn't include inttypes.h explicitly. This makes it easier to use it from vscclient (part of libcacard).
2011-04-01trace: move trace objects from Makefile to Makefile.objsAlon Levy
2011-04-01net: Improve the warnings for dubious command line option combinationsPeter Maydell
Improve the warnings we give if the user specified a combination of -net options which don't make much sense: * Don't warn about anything if the config is the implicit default "-net user -net nic" rather than one specified by the user (this will only kick in for boards with no NIC or if CONFIG_SLIRP is not set) * Diagnose the case where the user asked for NICs which the board didn't instantiate (for example where the user asked for two NICs but the board only supports one) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01hw/versatilepb, realview: Fix condition for instantiation of onboard NICPeter Maydell
Correct the condition determining whether we instantiate the onboard NIC or a PCI card NIC on VersatilePB and Realview boards. This was broken in two ways: (1) if the user asked for two default NICs ("-net nic -net nic") we would crash trying to strcmp() a NULL pointer (2) if the user asked for two NICs explicitly of the same model as the onboard NIC (eg "-net nic,model=smc91c111 -net nic,model=smc91c111") we would try to instantiate two onboard NICs at the same address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01pcnet: Fix sign extension: make ipxe work with >2G RAMMichael Brown
The problem is with definitions in hw/pcnet.c such as: #define CSR_CRDA(S) ((S)->csr[28] | ((S)->csr[29] << 16)) "(S)->csr[29]" is a uint16_t, but "(S)->csr[29] << 16" gets promoted to int, so the overall CSR_CRDA(s) is a (signed) int rather than a uint32_t. This then gets assigned to a uint64_t using target_phys_addr_t crda = CSR_CRDA(s); so when (S)->csr[29] has the high bit set, we end up with crda=0xffffffffxxxxxxxx. From: Michael Brown <mcb30@ipxe.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01target-arm: Don't leak TCG temp for UNDEFs in Neon load/store spacePeter Maydell
Move the allocation and freeing of the TCG temp used for the address for Neon load/store instructions so that we don't allocate the temporary until we've done enough decoding to know that the instruction is not an UNDEF pattern; this avoids leaking the TCG temp in these cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01target-arm: Fix VLD of single element to all lanesPeter Maydell
Fix several bugs in VLD of single element to all lanes: The "single element to all lanes" form of VLD1 differs from those for VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element should be written to one or two Dregs (rather than being a register stride). Handle this by special-casing VLD1 rather than trying to have one loop which deals with both VLD1 and 2/3/4. Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing. UNDEF for the invalid size and alignment combinations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01Fix net_check_clients warnings: make it per vlan.Tristan Gingold
Signed-off-by: Tristan Gingold <gingold@adacore.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01vnc: added missing name->keysym pairs for Polish national charactersLeszek Grzegorek
There are no { name, keysym } values in name2keysym[] array for Polish national characters so "-k pl" option has no effect. Signed-off-by: Leszek Grzegorek <leszek.grzegorek@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01get rid of private bitmap functions in block/sheepdog.c, use generic onesMichael Tokarev
qemu now has generic bitmap functions, so don't redefine them in sheepdog.c, use common header instead. A small cleanup. Here's only one function which is actually used in sheepdog and gets replaced with a generic one (simplified): - static inline int test_bit(int nr, const volatile unsigned long *addr) + static inline int test_bit(int nr, const unsigned long *addr) { - return ((1UL << (nr % BITS_PER_LONG)) & ((unsigned long*)addr)[nr / BITS_PER_LONG])) != 0; + return 1UL & (addr[nr / BITS_PER_LONG] >> (nr & (BITS_PER_LONG-1))); } The body is equivalent, but the argument is not: there's "volatile" in there. Why it is used for - I'm not sure. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Acked-by: MORITA Kazutaka <morita.kazutaka@lab.ntt.co.jp> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01lsi53c895a: add support for ABORT messagesBernhard Kohl
If these messages are not handled correctly the guest driver may hang. Always mandatory: - ABORT - BUS DEVICE RESET Mandatory if tagged queuing is implemented (which disks usually do): - ABORT TAG - CLEAR QUEUE Signed-off-by: Bernhard Kohl <bernhard.kohl@nsn.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01fix build errors when we enable acpi_piix4 debugWen Congyang
I enable acpi_piix4 debug, and got the following build errors: # make CC libhw64/acpi_piix4.o cc1: warnings being treated as errors /home/wency/source/qemu/hw/acpi_piix4.c: In function ‘pm_ioport_write’: /home/wency/source/qemu/hw/acpi_piix4.c:193: error: format ‘%04x’ expects type ‘unsigned int’, but argument 2 has type ‘uint64_t’ /home/wency/source/qemu/hw/acpi_piix4.c:193: error: format ‘%04x’ expects type ‘unsigned int’, but argument 3 has type ‘uint64_t’ /home/wency/source/qemu/hw/acpi_piix4.c: In function ‘pm_ioport_read’: /home/wency/source/qemu/hw/acpi_piix4.c:219: error: format ‘%04x’ expects type ‘unsigned int’, but argument 2 has type ‘uint64_t’ make[1]: *** [acpi_piix4.o] Error 1 make: *** [subdir-libhw64] Error 2 Signed-off-by: Wen Congyang <wency@cn.fujitsu.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01ui/sdl: Load optional QEMU iconStefan Weil
Load an optional QEMU icon file. If there is no icon file named qemu.bmp in QEMU's default search path, QEMU will run with the usual system default icon. A matching icon file will be loaded and used by X Windows managers or MS Windows while a QEMU instance is running. SDL requires icon files in 32x32x4 bmp format. Cc: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01pc-bios/spapr-rtas.bin: remove executable flagAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01Add SLOF-based partition firmware for pSeries machine, allowing more boot ↵David Gibson
options Currently, the emulated pSeries machine requires the use of the -kernel parameter in order to explicitly load a guest kernel. This means booting from the virtual disk, cdrom or network is not possible. This patch addresses this limitation by inserting a within-partition firmware image (derived from the "SLOF" free Open Firmware project). If -kernel is not specified, qemu will now load the SLOF image, which has access to the qemu boot device list through the device tree, and can boot from any of the usual virtual devices. In order to support the new firmware, an extension to the emulated machine/hypervisor is necessary. Unlike Linux, which expects multi-CPU entry to be handled kexec() style, the SLOF firmware expects only one CPU to be active at entry, and to use a hypervisor RTAS method to enable the other CPUs one by one. This patch also implements this 'start-cpu' method, so that SLOF can start the secondary CPUs and marshal them into the kexec() holding pattern ready for entry into the guest OS. Linux should, and in the future might directly use the start-cpu method to enable initially disabled CPUs, but for now it does require kexec() entry. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PAPR VPA functions for pSeries shared processor partitionsDavid Gibson
Shared-processor partitions are those where a CPU is time-sliced between partitions, rather than being permanently dedicated to a single partition. qemu emulated partitions, since they are just scheduled with the qemu user process, behave mostly like shared processor partitions. In order to better support shared processor partitions (splpar), PAPR defines the "VPA" (Virtual Processor Area), a shared memory communication channel between the hypervisor and partitions. There are also two additional shared memory communication areas for specialized purposes associated with the VPA. A VPA is not essential for operating an splpar, though it can be necessary for obtaining accurate performance measurements in the presence of runtime partition switching. Most importantly, however, the VPA is a prerequisite for PAPR's H_CEDE, hypercall, which allows a partition OS to give up it's shared processor timeslices to other partitions when idle. This patch implements the VPA and H_CEDE hypercalls in qemu. We don't implement any of the more advanced statistics which can be communicated through the VPA. However, this is enough to make normal pSeries kernels do an effective power-save idle on an emulated pSeries, significantly reducing the host load of a qemu emulated pSeries running an idle guest OS. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add a PAPR TCE-bypass mechanism for the pSeries machineBen Herrenschmidt
Usually, PAPR virtual IO devices use a virtual IOMMU mechanism, TCEs, to mediate all DMA transfers. While this is necessary for some sorts of operation, it can be complex to program and slow for others. This patch implements a mechanism for bypassing TCE translation, treating "IO" addresses as plain (guest) physical memory addresses. This has two main uses: * Simple, but 64-bit aware programs like firmwares can use the VIO devices without the complexity of TCE setup. * The guest OS can optionally use the TCE bypass to improve performance in suitable situations. The mechanism used is a per-device flag which disables TCE translation. The flag is toggled with some (hypervisor-implemented) RTAS methods. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PAPR virtual SCSI interface (ibmvscsi)Ben Herrenschmidt
This patch implements the infrastructure and hypercalls necessary for the PAPR specified Virtual SCSI interface. This is the normal method for providing (virtual) disks to PAPR partitions. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PAPR CRQ hypercallsBen Herrenschmidt
This patch implements the infrastructure and hypercalls necessary for the PAPR specified CRQ (Command Request Queue) mechanism. This general request queueing system is used by many of the PAPR virtual IO devices, including the virtual scsi adapter. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement sPAPR Virtual LAN (ibmveth)David Gibson
This patch implements the PAPR specified Inter Virtual Machine Logical LAN; that is the virtual hardware used by the Linux ibmveth driver. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement TCE translation for sPAPR VIODavid Gibson
This patch implements the necessary infrastructure and hypercalls for sPAPR's TCE (Translation Control Entry) IOMMU mechanism. This is necessary for all virtual IO devices which do DMA (i.e. nearly all of them). Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add (virtual) interrupt to PAPR virtual tty deviceDavid Gibson
Now that we have implemented the PAPR "xics" virtualized interrupt controller, we can add interrupts in PAPR VIO devices. This patch adds interrupt support to the PAPR virtual tty/console device. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add PAPR H_VIO_SIGNAL hypercall and infrastructure for VIO interruptsDavid Gibson
This patch adds infrastructure to support interrupts from PAPR virtual IO devices. This includes correctly advertising those interrupts in the device tree, and implementing the H_VIO_SIGNAL hypercall, used to enable and disable individual device interrupts. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement the PAPR (pSeries) virtualized interrupt controller (xics)David Gibson
PAPR defines an interrupt control architecture which is logically divided into ICS (Interrupt Control Presentation, each unit is responsible for presenting interrupts to a particular "interrupt server", i.e. CPU) and ICS (Interrupt Control Source, each unit responsible for one or more hardware interrupts as numbered globally across the system). All PAPR virtual IO devices expect to deliver interrupts via this mechanism. In Linux, this interrupt controller system is handled by the "xics" driver. On pSeries systems, access to the interrupt controller is virtualized via hypercalls and RTAS methods. However, the virtualized interface is very similar to the underlying interrupt controller hardware, and similar PICs exist un-virtualized in some other systems. This patch implements both the ICP and ICS sides of the PAPR interrupt controller. For now, only the hypercall virtualized interface is provided, however it would be relatively straightforward to graft an emulated register interface onto the underlying interrupt logic if we want to add a machine with a hardware ICS/ICP system in the future. There are some limitations in this implementation: it is assumed for now that only one instance of the ICS exists, although a full xics system can have several, each responsible for a different group of hardware irqs. ICP/ICS can handle both level-sensitve (LSI) and message signalled (MSI) interrupt inputs. For now, this implementation supports only MSI interrupts, since that is used by PAPR virtual IO devices. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement assorted pSeries hcalls and RTAS methodsDavid Gibson
This patch adds several small utility hypercalls and RTAS methods to the pSeries platform emulation. Specifically: * 'display-character' rtas call This just prints a character to the console, it's occasionally used for early debug of the OS. The support includes a hack to make this RTAS call respond on the normal token value present on real hardware, since some early debugging tools just assume this value without checking the device tree. * 'get-time-of-day' rtas call This one just takes the host real time, converts to the PAPR described format and returns it to the guest. * 'power-off' rtas call This one shuts down the emulated system. * H_DABR hypercall On pSeries, the DABR debug register is usually a hypervisor resource and virtualized through this hypercall. If the hypercall is not present, Linux will under some circumstances attempt to manipulate the DABR directly which will fail on this emulated machine. This stub implementation is enough to stop that behaviour, although it doesn't actually implement the requested DABR operations as yet. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement hcall based RTAS for pSeries machinesDavid Gibson
On pSeries machines, operating systems can instantiate "RTAS" (Run-Time Abstraction Services), a runtime component of the firmware which implements a number of low-level, infrequently used operations. On logical partitions under a hypervisor, many of the RTAS functions require hypervisor privilege. For simplicity, therefore, hypervisor systems typically implement the in-partition RTAS as just a tiny wrapper around a hypercall which actually implements the various RTAS functions. This patch implements such a hypercall based RTAS for our emulated pSeries machine. A tiny in-partition "firmware" calls a new hypercall, which looks up available RTAS services in a table. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Virtual hash page table handling on pSeries machineDavid Gibson
On pSeries logical partitions, excepting the old POWER4-style full system partitions, the guest does not have direct access to the hardware page table. Instead, the pagetable exists in hypervisor memory, and the guest must manipulate it with hypercalls. However, our current pSeries emulation more closely resembles the old style where the guest must set up and handle the pagetables itself. This patch converts it to act like a modern partition. This involves two things: first, the hash translation path is modified to permit the has table to be stored externally to the emulated machine's RAM. The pSeries machine init code configures the CPUs to use this mode. Secondly, we emulate the PAPR hypercalls for manipulating the external hashed page table. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement the bus structure for PAPR virtual IODavid Gibson
This extends the "pseries" (PAPR) machine to include a virtual IO bus supporting the PAPR defined hypercall based virtual IO mechanisms. So far only one VIO device is provided, the vty / vterm, providing a full console (polled only, for now). Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Start implementing pSeries logical partition machineDavid Gibson
This patch adds a "pseries" machine to qemu. This aims to emulate a logical partition on an IBM pSeries machine, compliant to the "PowerPC Architecture Platform Requirements" (PAPR) document. This initial version is quite limited, it implements a basic machine and PAPR hypercall emulation. So far only one hypercall is present - H_PUT_TERM_CHAR - so that a (write-only) console is available. Multiple CPUs are permitted, with SMP entry handled kexec() style. The machine so far more resembles an old POWER4 style "full system partition" rather than a modern LPAR, in that the guest manages the page tables directly, rather than via hypercalls. The machine requires qemu to be configured with --enable-fdt. The machine can (so far) only be booted with -kernel - i.e. no partition firmware is provided. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add POWER7 support for ppcDavid Gibson
This adds emulation support for the recent POWER7 cpu to qemu. It's far from perfect - it's missing a number of POWER7 features so far, including any support for VSX or decimal floating point instructions. However, it's close enough to boot a kernel with the POWER7 PVR. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Support 1T segments on ppcDavid Gibson
Traditionally, the "segments" used for the two-stage translation used on powerpc MMUs were 256MB in size. This was the only option on all hash page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page table based cpus. However, newer 64-bit cpus also permit 1TB segments This patch adds support for 1TB segment translation to the qemu code. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Better factor the ppc hash translation pathDavid Gibson
Currently the path handling hash page table translation in get_segment() has a mix of common and 32 or 64 bit specific code. However the division is not done terribly well which results in a lot of messy code flipping between common and divided paths. This patch improves the organization, consolidating several divided paths into one. This in turn allows simplification of some code in get_segment(), removing a number of ugly interim variables. This new factorization will also make it easier to add support for the 1T segments added in newer CPUs. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Use "hash" more consistently in ppc mmu codeDavid Gibson
Currently, get_segment() has a variable called hash. However it doesn't (quite) get the hash value for the ppc hashed page table. Instead it gets the hash shifted - effectively the offset of the hash bucket within the hash page table. As well, as being different to the normal use of plain "hash" in the architecture documentation, this usage necessitates some awkward 32/64 dependent masks and shifts which clutter up the path in get_segment(). This patch alters the code to use raw hash values through get_segment() including storing raw hashes instead of pte group offsets in the ctx structure. This cleans up the path noticeably. This does necessitate 32/64 dependent shifts when the hash values are taken out of the ctx structure and used, but those paths already have 32/64 bit variants so this is less awkward than it was in get_segment(). Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Parse SDR1 on mtspr instead of at translate timeDavid Gibson
On ppc machines with hash table MMUs, the special purpose register SDR1 contains both the base address of the encoded size (hashed) page tables. At present, we interpret the SDR1 value within the address translation path. But because the encodings of the size for 32-bit and 64-bit are different this makes for a confusing branch on the MMU type with a bunch of curly shifts and masks in the middle of the translate path. This patch cleans things up by moving the interpretation on SDR1 into the helper function handling the write to the register. This leaves a simple pre-sanitized base address and mask for the hash table in the CPUState structure which is easier to work with in the translation path. This makes the translation path more readable. It addresses the FIXME comment currently in the mtsdr1 helper, by validating the SDR1 value during interpretation. Finally it opens the way for emulating a pSeries-style partition where the hash table used for translation is not mapped into the guests's RAM. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Clean up slb_lookup() functionDavid Gibson
The slb_lookup() function, used in the ppc translation path returns a number of slb entry fields in reference parameters. However, only one of the two callers of slb_lookup() actually wants this information. This patch, therefore, makes slb_lookup() return a simple pointer to the located SLB entry (or NULL), and the caller which needs the fields can extract them itself. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Correct ppc popcntb logic, implement popcntw and popcntdDavid Gibson
qemu already includes support for the popcntb instruction introduced in POWER5 (although it doesn't actually allow you to choose POWER5). However, the logic is slightly incorrect: it will generate results truncated to 32-bits when the CPU is in 32-bit mode. This is not normal for powerpc - generally arithmetic instructions on a 64-bit powerpc cpu will generate full 64 bit results, it's just that only the low 32 bits will be significant for condition codes. This patch corrects this nit, which actually simplifies the code slightly. In addition, this patch implements the popcntw and popcntd instructions added in POWER7, in preparation for allowing POWER7 as an emulated CPU. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement missing parts of the logic for the POWER PURRDavid Gibson
The PURR (Processor Utilization Resource Register) is a register found on recent POWER CPUs. The guts of implementing it at least enough to get by are already present in qemu, however some of the helper functions needed to actually wire it up are missing. This patch adds the necessary glue, so that the PURR can be wired up when we implement newer POWER CPU targets which include it. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PowerPC slbmfee and slbmfev instructionsDavid Gibson
For a 64-bit PowerPC target, qemu correctly implements translation through the segment lookaside buffer. Likewise it supports the slbmte instruction which is used to load entries into the SLB. However, it does not emulate the slbmfee and slbmfev instructions which read SLB entries back into registers. Because these are only occasionally used in guests (mostly for debugging) we get away with it. However, given the recent SLB cleanups, it becomes quite easy to implement these, and thereby allow, amongst other things, a guest Linux to use xmon's command to dump the SLB. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Add a hook to allow hypercalls to be emulated on PowerPCDavid Gibson
PowerPC and POWER chips since the POWER4 and 970 have a special hypervisor mode, and a corresponding form of the system call instruction which traps to the hypervisor. qemu currently has stub implementations of hypervisor mode. That is, the outline is there to allow qemu to run a PowerPC hypervisor under emulation. There are a number of details missing so this won't actually work at present, but the idea is there. What there is no provision at all, is for qemu to instead emulate the hypervisor itself. That is to have hypercalls trap into qemu and their result be emulated from qemu, rather than running hypervisor code within the emulated system. Hypervisor hardware aware KVM implementations are in the works and it would be useful for debugging and development to also allow full emulation of the same para-virtualized guests as such a KVM. Therefore, this patch adds a hook which will allow a machine to set up emulation of hypervisor calls. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Allow qemu_devtree_setprop() to take arbitrary valuesDavid Gibson
Currently qemu_devtree_setprop() expects the new property value to be given as a uint32_t *. While property values consisting of u32s are common, in general they can have any bytestring value. Therefore, this patch alters the function to take a void * instead, allowing callers to easily give anything as the property value. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Clean up PowerPC SLB handling codeDavid Gibson
Currently the SLB information when emulating a PowerPC 970 is storeed in a structure with the unhelpfully named fields 'tmp' and 'tmp64'. While the layout in these fields does match the description of the SLB in the architecture document, it is not convenient either for looking up the SLB, or for emulating the slbmte instruction. This patch, therefore, reorganizes the SLB entry structure to be divided in the the "ESID related" and "VSID related" fields as they are divided in instructions accessing the SLB. In addition to making the code smaller and more readable, this will make it easier to implement for the 1TB segments used in more recent PowerPC chips. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01target-ppc: ext32u instead of andi with constantAurelien Jarno
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-03-31lm32: use lookup table for opcodesMichael Walle
Instead of a for loop use a faster lookup table. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-31lm32: rename raise opcode to scallMichael Walle
To be consistent with the new reference manual. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-29add a service to reap zombies, use it in SLIRPPaolo Bonzini
SLIRP -smb support wants to fork a process and forget about reaping it. To please it, add a generic service to register a process id and let QEMU reap it. In the future it could be enhanced to pass a status, but this would be unused. With this in place, the SIGCHLD signal handler would not stomp on pclose anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-29extract I/O handler lists to iohandler.cPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-28vhost: fix dirty page handlingMichael S. Tsirkin
vhost was passing a physical address to cpu_physical_memory_set_dirty, which is wrong: we need to translate to ram address first. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Note: this lead to crashes during migration, so the patch is needed on the stable branch too.
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-27 17:15:43 +0000