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2019-03-12mac_newworld: use node name instead of alias name for hd device in ↵Mark Cave-Ayland
FWPathProvider When using -drive to configure the hd drive for the New World machine, the node name "disk" should be used instead of the "hd" alias. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307212058.4890-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12mac_oldworld: use node name instead of alias name for hd device in ↵Mark Cave-Ayland
FWPathProvider When using -drive to configure the hd drive for the Old World machine, the node name "disk" should be used instead of the "hd" alias. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307212058.4890-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and ↵Mark Cave-Ayland
set_cpu_vsr{l,h}() Now that all VSX registers are stored in host endian order, there is no need to go via different accessors depending upon the register number. Instead we introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}(). This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the new vsr64_offset() function to more clearly express the relationship between the VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-8-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: switch fpr/vsrl registers so all VSX registers are in host ↵Mark Cave-Ayland
endian order When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: improve avr64_offset() and use it to simplify ↵Mark Cave-Ayland
get_avr64()/set_avr64() By using the VsrD macro in avr64_offset() the same offset calculation can be used regardless of the host endian. This allows get_avr64() and set_avr64() to be simplified accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-6-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce avr_full_offset() functionMark Cave-Ayland
All TCG vector operations require pointers to the base address of the vector rather than separate access to the top and bottom 64-bits. Convert the VMX TCG instructions to use a new avr_full_offset() function instead of avr64_offset() which can then itself be written as a simple wrapper onto vsr_full_offset(). This same function can also reused in cpu_avr_ptr() to avoid having more than one copy of the offset calculation logic. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-5-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: move Vsr* macros from internal.h to cpu.hMark Cave-Ayland
It isn't possible to include internal.h from cpu.h so move the Vsr* macros into cpu.h alongside the other VMX/VSX register access functions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-4-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce single vsrl_offset() functionMark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a single vsrl_offset() function. This commit also renames the existing get_vsr()/set_vsr() functions to get_vsrl()/set_vsrl() which better describes their purpose. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: introduce single fpr_offset() functionMark Cave-Ayland
Instead of having multiple copies of the offset calculation logic, move it to a single fpr_offset() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190307180520.13868-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12spapr_iommu: Do not replay mappings from just created DMA windowAlexey Kardashevskiy
On sPAPR vfio_listener_region_add() is called in 2 situations: 1. a new listener is registered from vfio_connect_container(); 2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window(). In both cases vfio_listener_region_add() calls memory_region_iommu_replay() to notify newly registered IOMMU notifiers about existing mappings which is totally desirable for case 1. However for case 2 it is nothing but noop as the window has just been created and has no valid mappings so replaying those does not do anything. It is barely noticeable with usual guests but if the window happens to be really big, such no-op replay might take minutes and trigger RCU stall warnings in the guest. For example, a upcoming GPU RAM memory region mapped at 64TiB (right after SPAPR_PCI_LIMIT) causes a 64bit DMA window to be at least 128TiB which is (128<<40)/0x10000=2.147.483.648 TCEs to replay. This mitigates the problem by adding an "skipping_replay" flag to sPAPRTCETable and defining sPAPR own IOMMU MR replay() hook which does exactly the same thing as the generic one except it returns early if @skipping_replay==true. Another way of fixing this would be delaying replay till the very first H_PUT_TCE but this does not work if in-kernel H_PUT_TCE handler is enabled (a likely case). When "ibm,create-pe-dma-window" is complete, the guest will map only required regions of the huge DMA window. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190307050518.64968-2-aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: psi: add a reset handlerCédric Le Goater
Reset all regs but keep the MMIO BAR enabled as it is at realize time. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-14-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: psi: add a PSIHB_REG macroCédric Le Goater
This is a simple helper to translate XSCOM addresses to MMIO addresses Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-13-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: fix logging primitives using OxCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-12-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/xive: activate HV supportCédric Le Goater
The NSR register of the HV ring has a different, although similar, bit layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts reserved for HW bringup and the POOL bit is used when signaling a group of VPs. This is not currently implemented in Linux but it is in pHyp. The most important special commands on the HV TIMA page are added to let the core manage interrupts : acking and changing the CPU priority. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-10-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: introduce a new pic_print_info() operation to the chip modelCédric Le Goater
The POWER9 and POWER8 processors have different interrupt controllers, and reporting their state requires calling different helper routines. However, the interrupt presenters are still handled in the higher level pic_print_info() routine because they are not related to the chip. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: introduce a new dt_populate() operation to the chip modelCédric Le Goater
The POWER9 and POWER8 processors have a different set of devices and a different device tree layout. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: add a XIVE interrupt controller model for POWER9Cédric Le Goater
This is a simple model of the POWER9 XIVE interrupt controller for the PowerNV machine which only addresses the needs of the skiboot firmware. The PowerNV model reuses the common XIVE framework developed for sPAPR as the fundamentals aspects are quite the same. The difference are outlined below. The controller initial BAR configuration is performed using the XSCOM bus from there, MMIO are used for further configuration. The MMIO regions exposed are : - Interrupt controller registers - ESB pages for IPIs and ENDs - Presenter MMIO (Not used) - Thread Interrupt Management Area MMIO, direct and indirect The virtualization controller MMIO region containing the IPI ESB pages and END ESB pages is sub-divided into "sets" which map portions of the VC region to the different ESB pages. These are modeled with custom address spaces and the XiveSource and XiveENDSource objects are sized to the maximum allowed by HW. The memory regions are resized at run-time using the configuration of EDT set translation table provided by the firmware. The XIVE virtualization structure tables (EAT, ENDT, NVTT) are now in the machine RAM and not in the hypervisor anymore. The firmware (skiboot) configures these tables using Virtual Structure Descriptor defining the characteristics of each table : SBE, EAS, END and NVT. These are later used to access the virtual interrupt entries. The internal cache of these tables in the interrupt controller is updated and invalidated using a set of registers. Still to address to complete the model but not fully required is the support for block grouping. Escalation support will be necessary for KVM guests. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-7-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: change the CPU machine_data presenter type to Object *Cédric Le Goater
The POWER9 PowerNV machine will use a XIVE interrupt presenter type. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/pnv: export the xive_router_notify() routineCédric Le Goater
The PowerNV machine with need to encode the block id in the source interrupt number before forwarding the source event notification to the Router. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/xive: export the TIMA memory accessorsCédric Le Goater
The PowerNV machine can perform indirect loads and stores on the TIMA on behalf of another CPU. Give the controller the possibility to call the TIMA memory accessors with a XiveTCTX of its choice. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc: externalize ppc_get_vcpu_by_pir()Cédric Le Goater
We will use it to get the CPU interrupt presenter in XIVE when the TIMA is accessed from the indirect page. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12ppc/xive: hardwire the Physical CAM line of the thread contextCédric Le Goater
By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12PPC: E500: Add FSL I2C controller and integrate RTC with itAndrew Randrianasulu
Original commit message: This patch adds an emulation model for i2c controller found on most of the FSL SoCs. It also integrates the RTC (ds1338) that sits on the i2c Bus with e500 machine model. Patch was originally written by Amit Singh Tomar <amit.tomar@freescale.com> see http://patchwork.ozlabs.org/patch/431475/ I only fixed it enough for application on top of current qemu master 20b084c4b1401b7f8fbc385649d48c67b6f43d44, and hopefully fixed checkpatch errors Tested by booting Linux kernel 4.20.12. Now e500 machine doesn't need network time protocol daemon because it will have working RTC (before all timestamps on files were from 2016) Signed-off-by: Amit Singh Tomar <amit.tomar@freescale.com> Signed-off-by: Andrew Randrianasulu <randrianasulu@gmail.com> Message-Id: <20190306102812.28972-1-randrianasulu@gmail.com> [dwg: Add Kconfig stanza to define the new symbol, update MAINTAINERS] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Enable H_PAGE_INIT in-kernel handlingSuraj Jitindar Singh
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest memory. Enable the in-kernel H_PAGE_INIT handler. The in-kernel handler takes half the time to complete compared to handling the H_CALL in userspace. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190306060608.19935-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit)David Gibson
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and hence of type hwaddr which is 64-bit. Previously it wasn't marked as such which means that it could be treated as 32-bit. That will work in some circumstances but if multiplied by another 32-bit value it could lead to a 32-bit overflow and an incorrect result. One specific instance of this in spapr_lmb_dt_populate() was spotted by Coverity (CID 1399145). Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Clear partition table entry when allocating hash tableSuraj Jitindar Singh
If we allocate a hash page table then we know that the guest won't be using process tables, so set the partition table entry maintained for the guest to zero. If this isn't done, then the guest radix bit will remain set in the entry. This means that when the guest calls H_REGISTER_PROCESS_TABLE there will be a mismatch between then flags and the value in spapr->patb_entry, and the call will fail. The guest will then panic: Failed to register process table (rc=-4) kernel BUG at arch/powerpc/platforms/pseries/lpar.c:959 The result being that it isn't possible to boot a hash guest on a P9 system. Also fix a bug in the flags parsing in h_register_process_table() which was introduced by the same patch, and simplify the handling to make it less likely that errors will be introduced in the future. The effect would have been setting the host radix bit LPCR_HR for a hash guest using process tables, which currently isn't supported and so couldn't have been triggered. Fixes: 00fd075e18 "target/ppc/spapr: Set LPCR:HR when using Radix mode" Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190305022102.17610-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12PPC: E500: Update u-boot to v2019.01Alexander Graf
Quite a while has passed since we last updated U-Boot for e500. This patch bumps it to the last released version 2019.01 to make sure users don't feel like they're using out of date software. Signed-off-by: Alexander Graf <agraf@csgraf.de> Message-Id: <20190304103930.16319-1-agraf@csgraf.de> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Refactor kvm_handle_debugFabiano Rosas
There are four scenarios being handled in this function: - single stepping - hardware breakpoints - software breakpoints - fallback (no debug supported) A future patch will add code to handle specific single step and software breakpoints cases so let's split each scenario into its own function now to avoid hurting readability. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-5-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Move handling of hardware breakpoints to a separate functionFabiano Rosas
This is in preparation for a refactoring of the kvm_handle_debug function in the next patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20190228225759.21328-4-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Move exception vector offset computation into a functionFabiano Rosas
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-2-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine typeSuraj Jitindar Singh
There are currently 3 mitigations the availability of which is controlled by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these mitigations by default for the pseries-4.0 machine type. By now machine firmware should have been upgraded to allow these settings. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301044609.9626-3-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcgSuraj Jitindar Singh
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the availability of certain mitigations to the guest. These haven't been implemented under TCG, it is unlikely they ever will be, and it is unclear as to whether they even need to be. As such, make failure to apply these capabilities under TCG non-fatal. Instead we print a warning message to the user but still allow the guest to continue. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301044609.9626-2-sjitindarsingh@gmail.com> [dwg: Small style fix] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Add SPAPR_CAP_CCF_ASSISTSuraj Jitindar Singh
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate the requirement for a hw-assisted version of the count cache flush workaround. The count cache flush workaround is a software workaround which can be used to flush the count cache on context switch. Some revisions of hardware may have a hardware accelerated flush, in which case the software flush can be shortened. This cap is used to set the availability of such hardware acceleration for the count cache flush routine. The availability of such hardware acceleration is indicated by the H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Add workaround option to SPAPR_CAP_IBSSuraj Jitindar Singh
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability for mitigations for indirect branch speculation. Currently the available values are broken (default), fixed-ibs (fixed by serialising indirect branches) and fixed-ccd (fixed by diabling the count cache). Introduce a new value for this capability denoted workaround, meaning that software can work around the issue by flushing the count cache on context switch. This option is available if the hypervisor sets the H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-1-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Enable the large decrementer for pseries-4.0Suraj Jitindar Singh
Enable the large decrementer by default for the pseries-4.0 machine type. It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus since they don't support the large decrementer. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301024317.22137-4-sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Implement large decrementer support for KVMSuraj Jitindar Singh
Implement support to allow KVM guests to take advantage of the large decrementer introduced on POWER9 cpus. To determine if the host can support the requested large decrementer size, we check it matches that specified in the ibm,dec-bits device-tree property. We also need to enable it in KVM by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-3-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc: Implement large decrementer support for TCGSuraj Jitindar Singh
Prior to POWER9 the decrementer was a 32-bit register which decremented with each tick of the timebase. From POWER9 onwards the decrementer can be set to operate in a mode called large decrementer where it acts as a n-bit decrementing register which is visible as a 64-bit register, that is the value of the decrementer is sign extended to 64 bits (where n is implementation dependant). The mode in which the decrementer operates is controlled by the LPCR_LD bit in the logical paritition control register (LPCR). >From POWER9 onwards the HDEC (hypervisor decrementer) was enlarged to h-bits, also sign extended to 64 bits (where h is implementation dependant). Note this isn't configurable and is always enabled. On POWER9 the large decrementer and hdec are both 56 bits, as represented by the lrg_decr_bits cpu class property. Since they are the same size we only add one property for now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTERSuraj Jitindar Singh
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the availability of the large decrementer for a guest. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301024317.22137-1-sjitindarsingh@gmail.com> [dwg: Trivial style fix] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12Revert "spapr: support memory unplug for qtest"Greg Kurz
Commit b8165118f52c broke CPU hotplug tests for old machine types: $ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test -m=slow /ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-3.0/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.10/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.11/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.12/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.9/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.7/device-add/2x3x1&maxcpus=6: ** ERROR:/home/thuth/devel/qemu/hw/ppc/spapr_events.c:313:rtas_event_log_to_source: assertion failed: (source->enabled) Broken pipe /home/thuth/devel/qemu/tests/libqtest.c:143: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped) Aborted (core dumped) The approach of faking the availability of OV5_HP_EVT causes the code to assume the hotplug event source is enabled, which is wrong for older machines. We've now fixed CAS under qtest with a different approach. Therefore, this reverts commit b8165118f52ce5ee88565d3cec83d30374efdc96. A subsequent patch will address the problem of CAS under qtest from a different angle. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155146875097.147873.1732264036668112686.stgit@bahia.lan> Tested-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12spapr: Simulate CAS for qtestGreg Kurz
The RTAS event hotplug code for machine types 2.8 and newer depends on the CAS negotiated ov5 in order to work properly. However, there's no CAS when running under qtest. There has been a tentative to trick the code by faking the OV5_HP_EVT bit, but it turned out to break other assumptions in the code and the change got reverted. Go for a more general approach and simulate a CAS when running under qtest. For simplicity, this pseudo CAS simple simulates the case where the guest supports the same features as the machine. It is done at reset time, just before we reset the DRCs, which could potentially exercise the unplug code. This allows to test unplug on spapr with both older and newer machine types. Suggested-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155146875704.147873.10563808578795890265.stgit@bahia.lan> Tested-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12vfio/spapr: Rename local systempagesize variableAlexey Kardashevskiy
The "systempagesize" name suggests that it is the host system page size while it is the smallest page size of memory backing the guest RAM so let's rename it to stop confusion. This should cause no behavioral change. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190227085149.38596-4-aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12vfio/spapr: Fix indirect levels calculationAlexey Kardashevskiy
The current code assumes that we can address more bits on a PCI bus for DMA than we really can but there is no way knowing the actual limit. This makes a better guess for the number of levels and if the kernel fails to allocate that, this increases the level numbers till succeeded or reached the 64bit limit. This adds levels to the trace point. This may cause the kernel to warn about failed allocation: [65122.837458] Failed to allocate a TCE memory, level shift=28 which might happen if MAX_ORDER is not large enough as it can vary: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/Kconfig?h=v5.0-rc2#n727 Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190227085149.38596-3-aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-11docs/interop/firmware.json: Prefer -machine to if=pflashMarkus Armbruster
The previous commit added a way to configure firmware with -blockdev rather than -drive if=pflash. Document it as the preferred way. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190308131445.17502-13-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-03-11pc: Support firmware configuration with -blockdevMarkus Armbruster
The PC machines put firmware in ROM by default. To get it put into flash memory (required by OVMF), you have to use -drive if=pflash,unit=0,... and optionally -drive if=pflash,unit=1,... Why two -drive? This permits setting up one part of the flash memory read-only, and the other part read/write. It also makes upgrading firmware on the host easier. Below the hood, it creates two separate flash devices, because we were too lazy to improve our flash device models to support sector protection. The problem at hand is to do the same with -blockdev somehow, as one more step towards deprecating -drive. Mapping -drive if=none,... to -blockdev is a solved problem. With if=T other than if=none, -drive additionally configures a block device frontend. For non-onboard devices, that part maps to -device. Also a solved problem. For onboard devices such as PC flash memory, we have an unsolved problem. This is actually an instance of a wider problem: our general device configuration interface doesn't cover onboard devices. Instead, we have a zoo of ad hoc interfaces that are much more limited. One of them is -drive, which we'd rather deprecate, but can't until we have suitable replacements for all its uses. Sadly, I can't attack the wider problem today. So back to the narrow problem. My first idea was to reduce it to its solved buddy by using pluggable instead of onboard devices for the flash memory. Workable, but it requires some extra smarts in firmware descriptors and libvirt. Paolo had an idea that is simpler for libvirt: keep the devices onboard, and add machine properties for their block backends. The implementation is less than straightforward, I'm afraid. First, block backend properties are *qdev* properties. Machines can't have those, as they're not devices. I could duplicate these qdev properties as QOM properties, but I hate that. More seriously, the properties do not belong to the machine, they belong to the onboard flash devices. Adding them to the machine would then require bad magic to somehow transfer them to the flash devices. Fortunately, QOM provides the means to handle exactly this case: add alias properties to the machine that forward to the onboard devices' properties. Properties need to be created in .instance_init() methods. For PC machines, that's pc_machine_initfn(). To make alias properties work, we need to create the onboard flash devices there, too. Requires several bug fixes, in the previous commits. We also have to realize the devices. More on that below. If the user sets pflash0, firmware resides in flash memory. pc_system_firmware_init() maps and realizes the flash devices. Else, firmware resides in ROM. The onboard flash devices aren't used then. pc_system_firmware_init() destroys them unrealized, along with the alias properties. The existing code to pick up drives defined with -drive if=pflash is replaced by code to desugar into the machine properties. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <87ftrtux81.fsf@dusky.pond.sub.org>
2019-03-11pc_sysfw: Pass PCMachineState to pc_system_firmware_init()Philippe Mathieu-Daudé
pc_system_firmware_init() parameter @isapc_ram_fw is PCMachineState member pci_enabled negated. The next commit will need more of PCMachineState. To prepare for that, pass a PCMachineState *, and drop the now redundant parameter @isapc_ram_fw. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20190308131445.17502-11-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2019-03-11pc_sysfw: Remove unused PcSysFwDevicePhilippe Mathieu-Daudé
This structure is not used since commit 6dd2a5c98a. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190308131445.17502-10-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2019-03-11pflash_cfi01: Add pflash_cfi01_get_blk() helperPhilippe Mathieu-Daudé
Add an helper to access the opaque struct PFlashCFI01. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20190308131445.17502-9-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2019-03-11vl: Create block backends before setting machine propertiesMarkus Armbruster
qemu-system-FOO's main() acts on command line arguments in its own idiosyncratic order. There's not much method to its madness. Whenever we find a case where one kind of command line argument needs to refer to something created for another kind later, we rejigger the order. Block devices get created long after machine properties get processed. Therefore, block device machine properties can be created, but not set. No such properties exist. But the next commit will create some. Time to rejigger again: create block devices earlier. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190308131445.17502-8-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2019-03-11vl: Factor configure_blockdev() out of main()Markus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190308131445.17502-7-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2019-03-11vl: Improve legibility of BlockdevOptions queueMarkus Armbruster
Give the queue head type a name: BlockdevOptionsQueue. Rename the queue entry type from BlockdevOptions_queue to BlockdevOptionsQueueEntry. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190308131445.17502-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>