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2015-06-21target-microblaze: Allow the stack protection to be disabledAlistair Francis
Microblaze stack protection is configurable and isn't always enabled. This patch allows the stack protection to be disabled from the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-06-21target-microblaze: Preserve the pvr registers during resetAlistair Francis
Move the Microblaze PVR registers to the end of the CPUMBState and preserve them during reset. This is similar to what the QEMU ARM model does with some of it's registers. This allows the Microblaze PVR registers to only be set once at realise instead of constantly at reset. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-06-21target-microblaze: Fix up indentationAlistair Francis
Fix up the incorrect indentation level in the helper_stackprot() function. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-06-21microblaze: s3adsp: Instantiate CPU using QOMPeter Crosthwaite
Instantiate and realise the CPU directly, rather than using cpu_mb_init. Microblazes cpu_model argument is a dummy so remove the default cpu_model set logic. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-06-19Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20150619' into staging target-arm queue: * support --semihosting-config,arg=value * Cortex-R5 support (including implementing them on the Zynq board) * Cortex-M4 support (without FPU) * enable vfio-calxeda-xgmac * don't reset ALIAS sysregs # gpg: Signature made Fri Jun 19 14:41:54 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150619: semihosting: add --semihosting-config arg sub-argument semihosting: create SemihostingConfig structure and semihost.h arm: xlnx-zynqmp: Add 2xCortexR5 CPUs arm: xlnx-zynqmp: Add boot-cpu property arm: xlnx-zynqmp: Preface CPU variables with "apu" target-arm: Add support for Cortex-R5 target-arm: Implement PMSAv7 MPU target-arm: Add registers for PMSAv7 target-arm/helper.c: define MPUIR register target-arm: Do not reset sysregs marked as ALIAS hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation target-arm: Add the Cortex-M4 CPU Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19semihosting: add --semihosting-config arg sub-argumentLeon Alrae
Add new "arg" sub-argument to the --semihosting-config allowing the user to pass multiple input arguments separately. It is required for example by UHI semihosting to construct argc and argv. Also, update ARM semihosting to support new option (at the moment it is the only target which cares about arguments). If the semihosting is enabled and no semihosting args have been specified, then fall back to -kernel/-append. The -append string is split on whitespace before initializing semihosting.argv[1..n]; this is different from what QEMU MIPS machines' pseudo-bootloaders do (i.e. argv[1] contains the whole -append), but is more intuitive from UHI user's point of view and Linux kernel just does not care as it concatenates argv[1..n] into single cmdline string anyway. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1434643256-16858-3-git-send-email-leon.alrae@imgtec.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae
Remove semihosting_enabled and semihosting_target and replace them with SemihostingConfig structure containing equivalent fields. The structure is defined in vl.c where it is actually set. Also introduce separate header file include/exec/semihost.h allowing to access semihosting config related stuff from target specific semihosting code. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434643256-16858-2-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19arm: xlnx-zynqmp: Add 2xCortexR5 CPUsPeter Crosthwaite
Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset (this is true of real hardware) by default or selectable as the boot processor. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19arm: xlnx-zynqmp: Add boot-cpu propertyPeter Crosthwaite
Add a string property that specifies the primary boot cpu. All CPUs except the one selected will start-powered-off. This allows for elf boots on any CPU, which prepares support for booting R5 elfs directly on the R5 processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19arm: xlnx-zynqmp: Preface CPU variables with "apu"Peter Crosthwaite
The CPUs currently supported by zynqmp are the APU (application processing unit) CPUs. There are other CPUs in Zynqmp so unqualified "cpus" in ambiguous. Preface the variables with "APU" accordingly, to prepare support adding the RPU (realtime processing unit) processors. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: ce32287fc365aea898465e981da3546a227e0811.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Add support for Cortex-R5Peter Crosthwaite
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU, and both thumb and ARM div instructions. Also implement dummy ATCM and BTCM. These CPs are defined for R5 but don't have a lot of meaning in QEMU yet. Raz them so the guest can proceed if they are read. The TCM registers will return a size of 0, indicating no TCM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: efe213163e6800578494aba864ac30329de4d396.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite
Unified MPU only. Uses ARM architecture major revision to switch between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains unsupported and is asserted against. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: dcb03cda6dd754c5cc6a962fa11f25089811e954.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite
Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 172cf135fbd8f5cea413c00e71cc1c3cac704744.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite
Define the MPUIR register for MPU supporting ARMv6 and onwards. Currently we only support unified MPU. The size of the unified MPU is defined via the number of "dregions". So just a single config is added to specify this size. (When split MPU is implemented we will add an extra iregions config). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 9f248950b803a08c8b3c978931663182f7e882e7.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov
cp_reg_reset() is called from g_hash_table_foreach() which does not define a specific ordering of the hash table iteration. Thus doing reset for registers marked as ALIAS would give an ambiguous result when resetvalue is different for original and alias registers. Exit cp_reg_reset() early when passed an alias register. Then clean up alias register definitions from needless resetvalue and resetfn. In particular, this fixes a bug in the handling of the PMCR register, which had different resetvalues for its 32 and 64-bit views. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1434554713-10220-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiationEric Auger
This patch allows the instantiation of the vfio-calxeda-xgmac device from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>"). A specialized device tree node is created for the guest, containing compat, dma-coherent, reg and interrupts properties. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434455898-17895-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19target-arm: Add the Cortex-M4 CPUAurelio C. Remonda
This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3, the main differences being the DSP instructions and an optional FPU. Only no-FPU cortex-M4 is implemented here, cortex-M4F is not because the core target-arm code doesn't support the M-profile FPU model yet. Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com> Message-id: 1434461850-4104-1-git-send-email-aurelioremonda@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20150619-1' ↵Peter Maydell
into staging cocoa queue: * Add Machine menu, with entries for pause, resume, reset, power down, and media change and eject for removable drives # gpg: Signature made Fri Jun 19 11:24:11 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-cocoa-20150619-1: ui/cocoa.m: Add machine menu items to change and eject removable drive media ui/cocoa.m: Add Reset and Power Down menu items to Machine menu ui/cocoa.m: Add Machine menu with pause and resume menu items Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio, pci fixes, enhancements Most notably this includes virtio cross-endian patches. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Fri Jun 19 11:18:05 2015 BST using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: vhost: enable vhost without without MSI-X pci: Don't register a specialized 'config_write' if default behavior is intended hw/core: rebase sysbus_get_fw_dev_path() to g_strdup_printf() vhost_net: re-enable when cross endian vhost-net: tell tap backend about the vnet endianness tap: fix non-linux build tap: add VNET_LE/VNET_BE operations vhost: set vring endianness for legacy virtio virtio: introduce virtio_legacy_is_cross_endian() linux-headers: sync vhost.h vhost-user: part of virtio Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19ui/cocoa.m: Add machine menu items to change and eject removable drive mediaJohn Arbuckle
Adds all removable devices to the Machine menu as a Change and Eject menu item pair. ide-cd0 would have a "Change ide-cd0..." and "Eject ide-cd0" menu items. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19ui/cocoa.m: Add Reset and Power Down menu items to Machine menuJohn Arbuckle
Add "Reset" and "Power Down" menu items to Machine menu. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19vhost: enable vhost without without MSI-XPankaj Gupta
We use vhostforce to enable vhost even if Guests don't have MSI-X support and we fall back to QEMU virtio-net. This gives a very small performance gain, but the disadvantage is that guest now controls which virtio code is running (qemu or vhost) so our attack surface is doubled. This patch will enable vhost unconditionally whenever it's requested. For compatibility, enable vhost when vhostforce is set, as well. Signed-off-by: Pankaj Gupta <pagupta@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com>
2015-06-19pci: Don't register a specialized 'config_write' if default behavior is intendedShmulik Ladkani
Few devices have their specialized 'config_write' methods which simply call 'pci_default_write_config' followed by a 'msix_write_config' or 'msi_write_config' calls, using exact same arguments. This is unnecessary as 'pci_default_write_config' already invokes 'msi_write_config' and 'msix_write_config'. Also, since 'pci_default_write_config' is the default 'config_write' handler, we can simply avoid the registration of these specialized versions. Cc: Leonid Shatz <leonid.shatz@ravellosystems.com> Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-19hw/core: rebase sysbus_get_fw_dev_path() to g_strdup_printf()Laszlo Ersek
This is done mainly for improving readability, and in preparation for the next patch, but Markus pointed out another bonus for the string being returned: "No arbitrary length limit. Before the patch, it's 39 characters, and the code breaks catastrophically when qdev_fw_name() is longer: the second snprintf() is called with its first argument pointing beyond path[], and its second argument underflowing to a huge size." Cc: qemu-stable@nongnu.org Signed-off-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-19vhost_net: re-enable when cross endianCédric Le Goater
Cross-endianness is now checked by the core vhost code. revert 371df9f5e0f1 "vhost-net: disable when cross-endian" Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> [ added commit message, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-19vhost-net: tell tap backend about the vnet endiannessGreg Kurz
The default behaviour for TAP/MACVTAP is to consider vnet as native endian. This patch handles the cases when this is not true: - virtio 1.0: always little-endian - legacy cross-endian Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-19tap: fix non-linux buildMichael S. Tsirkin
tap_fd_set_vnet_le/tap_fd_set_vnet_be was missing, fix it up. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
2015-06-19ui/cocoa.m: Add Machine menu with pause and resume menu itemsJohn Arbuckle
Add Machine menu to the Macintosh interface with pause and resume menu items. These items can either pause or resume execution of the guest operating system. Signed-off-by: John Arbuckle <programmingkidx@gmail.com> Message-id: 6D7AE6AA-0595-4FAD-AACF-9DFAB87248F0@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-19q35: Re-enable FDC on pc-q35-2.3 and olderEduardo Habkost
commit ea96bc629cbd52be98b2967a4b4f72e91dfc3ee4 doesn't match the patch submitted by Laszlo to qemu-devel. We reuse pc_q35_2_4_machine_options() inside pc_q35_2_3_machine_options(), so we need to undo the no_floppy change in pc_q35_2_3_machine_options(). (This discrepancy was due to a bad merge.) This restores the previous behavior where all the 2.3 and older machines had no_floppy=0. Reported-by: Ján Tomko <jtomko@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 1434646168-3100-1-git-send-email-ehabkost@redhat.com Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [PMM: mention that this was a merge issue, not a review issue] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-18Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2015-06-18' into ↵Peter Maydell
staging QAPI patches # gpg: Signature made Thu Jun 18 13:20:00 2015 BST using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-qapi-2015-06-18: qapi-types: Bury code dead since commit 6b5abc7 qapi-types: Split generate_fwd_builtin() off generate_fwd_struct() qapi-types: Drop unused members parameters qapi-types: Don't filter out expressions with 'gen' qapi: Catch and reject flat union branch of array type tests/qapi-schema: New flat union array branch test case qapi: Better separate the different kinds of helpers qapi: Move exprs checking from parse_schema() to check_exprs() qapi: Fix to reject stray 't', 'f' and 'n' qapi: Simplify inclusion cycle detection qapi: Fix file name in error messages for included files qapi: Improve a couple of confusing variable names qapi: Eliminate superfluous QAPISchema attribute input_dir qapi: Drop bogus command from docs MAINTAINERS: Fix up QAPI and QAPI schema file patterns Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-18qapi-types: Bury code dead since commit 6b5abc7Markus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi-types: Split generate_fwd_builtin() off generate_fwd_struct()Markus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi-types: Drop unused members parametersMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi-types: Don't filter out expressions with 'gen'Markus Armbruster
Useless, because it can only occur in commands, and we're not dealing with commands here. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Catch and reject flat union branch of array typeMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18tests/qapi-schema: New flat union array branch test caseMarkus Armbruster
The new test demonstrates another generator crash. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Better separate the different kinds of helpersMarkus Armbruster
Insert comments to separate sections dealing with parsing, semantic analysis, code generation, and so forth. Move helpers to their proper section. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Move exprs checking from parse_schema() to check_exprs()Markus Armbruster
To have expression semantic analysis in one place rather than two. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Fix to reject stray 't', 'f' and 'n'Markus Armbruster
Screwed up in commit e53188a. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Simplify inclusion cycle detectionMarkus Armbruster
We maintain a stack of filenames in include_hist for convenient cycle detection. As error_path() demonstrates, the same information is readily available in the expr_info, so just use that, and drop include_hist. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Fix file name in error messages for included filesMarkus Armbruster
We print the name as it appears in the include expression. Tools processing error messages want it relative to the working directory. Make it so. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Improve a couple of confusing variable namesMarkus Armbruster
old name new name ---------------------------- input_file fname input_relname fname input_fname abs_fname include_path incl_abs_fname parent_info incl_info Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Eliminate superfluous QAPISchema attribute input_dirMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18qapi: Drop bogus command from docsMarkus Armbruster
Commit 87a560c4 added it in the wrong place. Commit 59a2c4ce added it in the right place, but didn't remove it from the wrong place. Do that now. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18MAINTAINERS: Fix up QAPI and QAPI schema file patternsMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2015-06-18Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' ↵Peter Maydell
into staging Update OpenBIOS images # gpg: Signature made Wed Jun 17 20:06:06 2015 BST using RSA key ID AE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" * remotes/mcayland/tags/qemu-openbios-signed: Update OpenBIOS images Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-18vfio: fix build error on CentOS 5.7Leon Alrae
Include linux/vfio.h after sys/ioctl.h, just like in hw/vfio/common.c. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: Alex Williamson <alex.williamson@redhat.com> Message-id: 1434544500-22405-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-17Update OpenBIOS imagesMark Cave-Ayland
Update OpenBIOS images to SVN r1340 built from submodule. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2015-06-17tap: add VNET_LE/VNET_BE operationsGreg Kurz
The linux tap and macvtap backends can be told to parse vnet headers according to little or big endian. This is done through the TUNSETVNETLE and TUNSETVNETBE ioctls. This patch brings all the plumbing for QEMU to use these APIs. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-06-17vhost: set vring endianness for legacy virtioGreg Kurz
Legacy virtio is native endian: if the guest and host endianness differ, we have to tell vhost so it can swap bytes where appropriate. This is done through a vhost ring ioctl. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-02 21:36:49 +0000