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2022-05-03os-posix: replace pipe()+cloexec with g_unix_open_pipe(CLOEXEC)Marc-André Lureau
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-03tests: replace pipe() with g_unix_open_pipe(CLOEXEC)Marc-André Lureau
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2022-05-03qga: replace pipe() with g_unix_open_pipe(CLOEXEC)Marc-André Lureau
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2022-05-03util: replace pipe()+cloexec with g_unix_open_pipe()Marc-André Lureau
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-03Replace qemu_pipe() with g_unix_open_pipe()Marc-André Lureau
GLib g_unix_open_pipe() is essentially like qemu_pipe(), available since 2.30. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-03block: move fcntl_setfl()Marc-André Lureau
It is only used by block/file-posix.c, move it there. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-03Use g_unix_set_fd_nonblocking()Marc-André Lureau
API available since glib 2.30. It also preserves errno. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-03libqtest: split QMP part in libqmpMarc-André Lureau
This will help moving QAPI/QMP in a common subproject. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com>
2022-05-03tests: move libqtest.h back under qtest/Marc-André Lureau
Since commit a2ce7dbd917 ("meson: convert tests/qtest to meson"), libqtest.h is under libqos/ directory, while libqtest.c is still in qtest/. Move back to its original location to avoid mixing with libqos/. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
2022-05-03Use QEMU_SANITIZE_ADDRESSMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
2022-05-03Use QEMU_SANITIZE_THREADMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-01Merge tag 'pull-9p-20220501' of https://github.com/cschoenebeck/qemu into ↵Richard Henderson
staging 9pfs: various fixes * macOS: Fix recently (in QEMU 7.0) added 9p support for macOS hosts. * Tests: Fix inode sequencing in 'synth' driver. # -----BEGIN PGP SIGNATURE----- # # iQJLBAABCgA1FiEEltjREM96+AhPiFkBNMK1h2Wkc5UFAmJuhqEXHHFlbXVfb3Nz # QGNydWRlYnl0ZS5jb20ACgkQNMK1h2Wkc5U4fBAAofSRlDuxC0h2irHy0tRRGv+W # rH1gDVm0jzFChUumarUOs5/hZjG5C4H9nFA0g/6di9bSoiubtA839w/dDmUYV7Xn # S/8Jvauk/zZley1R1AKK5BEtOjJTlEYkbLqR1i9JPUrUk3Q9A+/f0FhgnW8NU2zu # KhqbzYZnUXb3P1RyRm4cTh9UCr904OI30mdqiM9U+oJag1Zd3us/Q9sPdqDCYs8e # vD4UXqG8c5UYpEN6C/ag2p3oJpAzpRa3CLkT5U59j/LhNgVtBPG/Pm5Q9qKHrxiN # 3p/+36NWLNXMtCKsU4Tf9TsA+tEB1G+QfObC5g8yM0e12dInW7K8KKUIOO7lE5Eq # a8aXZZC4yjW6y9vml0tC2E8p3n7n3r4MdLIrdY5VoOk72QLLBORq547DN/c5vt8A # Qsj2eZTvkrZNVmpQKpanwc8nsavslenFmQVVo+E6kuEOhTJpBeahsEx/ReH4D9rg # Hmq9O+xnPXodrj4DI1uqdwxN37A6bAn/4UAnQiPosnbzn+a6rZ3TZZ7x6ZZVwVub # MyPdWSwu0JujcD8Goina7f12tDOt2GaYrbegH4AG3B6kpMUQD6vwzcAFwZMP/0zZ # XMQnhR/lrvpsuBymuNA8cHRjccK6uGHxCEbstSsvKJCw0GqSonvTzMKY43HtgWmz # XjQe3jVk2+U5Aw8umTU= # =KBDF # -----END PGP SIGNATURE----- # gpg: Signature made Sun 01 May 2022 06:09:53 AM PDT # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * tag 'pull-9p-20220501' of https://github.com/cschoenebeck/qemu: 9pfs: fix qemu_mknodat() to always return -1 on error on macOS host 9pfs: fix removing non-existent POSIX ACL xattr on macOS host 9pfs: fix wrong errno being sent to Linux client on macOS host 9pfs: fix wrong encoding of rdev field in Rgetattr on macOS 9pfs: fix qemu_mknodat(S_IFSOCK) on macOS 9pfs: fix qemu_mknodat(S_IFREG) on macOS 9pfs: fix inode sequencing in 'synth' driver Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-019pfs: fix qemu_mknodat() to always return -1 on error on macOS hostChristian Schoenebeck
qemu_mknodat() is expected to behave according to its POSIX API, and therefore should always return exactly -1 on any error, and errno should be set for the actual error code. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <c714b5e1cae225ab7575242c45ee0fe4945eb6ad.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix removing non-existent POSIX ACL xattr on macOS hostChristian Schoenebeck
When mapped POSIX ACL is used, we are ignoring errors when trying to remove a POSIX ACL xattr that does not exist. On Linux hosts we would get ENODATA in such cases, on macOS hosts however we get ENOATTR instead. As we can be sure that ENOATTR is defined as being identical on Linux hosts (at least by qemu/xattr.h), it is safe to fix this issue by simply comparing against ENOATTR instead of ENODATA. This patch fixes e.g. a command on Linux guest like: cp --preserve=mode old new Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/2866993.yOYK24bMf6@silver/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <34f81e9bffd7a3e65fb7aab5b56c107bd0aac960.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix wrong errno being sent to Linux client on macOS hostChristian Schoenebeck
Linux and macOS only share some errno definitions with equal macro name and value. In fact most mappings for errno are completely different on the two systems. This patch converts some important errno values from macOS host to corresponding Linux errno values before eventually sending such error codes along with 'Rlerror' replies (if 9p2000.L is used that is). Not having translated errnos before violated the 9p2000.L protocol spec, which says: " size[4] Rlerror tag[2] ecode[4] ... ecode is a numerical Linux errno. " https://github.com/chaos/diod/wiki/protocol#lerror----return-error-code This patch fixes a bunch of misbehaviours when running a Linux client on macOS host. For instance this patch fixes: mount -t 9p -o posixacl ... on Linux guest if security_mode=mapped was used for 9p server, which refused to mount successfully, because macOS returned ENOATTR==93 when client tried to retrieve POSIX ACL xattrs, because errno 93 is defined as EPROTONOSUPPORT==93 on Linux, so Linux client believed that xattrs were not supported by filesystem on host in general. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/20220421124835.3e664669@bahia/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <b322ab298a62069e527d2b032028bdc9115afacd.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix wrong encoding of rdev field in Rgetattr on macOSChristian Schoenebeck
The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t, which is actually a system dependant type and therefore both the size and encoding of dev_t differ between macOS and Linux. So far we have sent 'rdev' to guest in host's dev_t format as-is, which caused devices to appear with wrong device numbers on guests running on macOS hosts, eventually leading to various misbehaviours on guest in conjunction with device files. This patch fixes this issue by converting the device number from host's dev_t format to Linux dev_t format. As 9p request 'Tgettattr' is exclusive to protocol version 9p2000.L, it should be fair to assume that 'rdev' field is assumed to be in Linux dev_t format by client as well. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/20220421093056.5ab1e7ed@bahia/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <b3a430c2c382ba69a7405e04c0b090ab0d86f17e.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix qemu_mknodat(S_IFSOCK) on macOSChristian Schoenebeck
mknod() on macOS does not support creating sockets, so divert to call sequence socket(), bind() and fchmodat() respectively if S_IFSOCK was passed with mode argument. Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <2e7b5ecd7a6d83a538db4e8a22d8fb03e9e0f06e.1651228001.git.qemu_oss@crudebyte.com> [C.S. - Use AT_SYMLINK_NOFOLLOW instead of AT_SYMLINK_NOFOLLOW_ANY. ] Link: https://lore.kernel.org/qemu-devel/3704033.BMyLRrx2Jx@silver/
2022-04-309pfs: fix qemu_mknodat(S_IFREG) on macOSChristian Schoenebeck
mknod() on macOS does not support creating regular files, so divert to openat_file() if S_IFREG is passed with mode argument. Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is equivalent to type S_IFREG". Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Will Cohen <wwcohen@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <3102ca936f88bc1f79d2a325e5bc68f48f54e6e3.1651228000.git.qemu_oss@crudebyte.com>
2022-04-309pfs: fix inode sequencing in 'synth' driverChristian Schoenebeck
The 'synth' driver's root node and the 'synth' driver's first subdirectory node falsely share the same inode number (zero), which makes it impossible for 9p clients (i.e. 9p test cases) to distinguish root node and first subdirectory from each other by comparing their QIDs (which are derived by 9p server from driver's inode numbers). Fix this issue by using prefix-increment instead of postfix-increment operator while generating new inode numbers for subdirectories and files. Link: https://lore.kernel.org/qemu-devel/3859307.hTDP4D0zbi@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <E1nTpyU-0000yR-9o@lizzy.crudebyte.com>
2022-04-29Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into ↵Richard Henderson
staging Second RISC-V PR for QEMU 7.1 * Improve device tree generation * Support configuarable marchid, mvendorid, mipid CSR values * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions * Fix incorrect PTE merge in walk_pte * Add TPM support to the virt board # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmJraeUACgkQIeENKd+X # cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok # Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA # d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc # v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35 # VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR # VvnUcI+p73qclCF7LkfL9c//xQT1iA== # =Xkoz # -----END PGP SIGNATURE----- # gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits) hw/riscv: Enable TPM backends hw/riscv: virt: Add device plug support hw/riscv: virt: Add support for generating platform FDT entries hw/riscv: virt: Create a platform bus hw/core: Move the ARM sysbus-fdt to core hw/riscv: virt: Add a machine done notifier target/riscv: add scalar crypto related extenstion strings to isa_string target/riscv: Fix incorrect PTE merge in walk_pte target/riscv: rvk: expose zbk* and zk* properties disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions target/riscv: rvk: add CSR support for Zkr target/riscv: rvk: add support for zksed/zksh extension target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension target/riscv: rvk: add support for sha256 related instructions in zknh extension target/riscv: rvk: add support for zkne/zknd extension in RV64 target/riscv: rvk: add support for zknd/zkne extension in RV32 crypto: move sm4_sbox from target/arm target/riscv: rvk: add support for zbkx extension target/riscv: rvk: add support for zbkc extension ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis
Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board. This was tested by first creating an emulated TPM device: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock Then launching QEMU with: -chardev socket,id=chrtpm,path=swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -device tpm-tis-device,tpmdev=tpm0 The TPM device can be seen in the memory tree and the generated device tree. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis
Add support for plugging in devices, this was tested with the TPM device. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis
Similar to the ARM virt machine add support for adding device tree entries for dynamically created devices. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis
Create a platform bus to allow dynamic devices to be connected. This is based on the ARM implementation. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/core: Move the ARM sysbus-fdt to coreAlistair Francis
The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices. The RISC-V virt machine can also benefit from this, so move the code to the core directory. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis
Move the binary and device tree loading code to the machine done notifier. This allows us to prepare for editing the device tree as part of the notifier. This is based on similar code in the ARM virt machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li
- add zbk* and zk* strings to isa_edata_arr Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: Fix incorrect PTE merge in walk_pteRalf Ramsauer
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this case, walk_pte will erroneously merge them. Enforce the split up, by tracking the virtual base address. Let's say we have the mapping: 0x81200000 -> 0x89623000 (4K) 0x8120f000 -> 0x89624000 (4K) Before, walk_pte would have shown: vaddr paddr size attr ---------------- ---------------- ---------------- ------- 0000000081200000 0000000089623000 0000000000002000 rwxu-ad as it only checks for subsequent paddrs. With this patch, it becomes: vaddr paddr size attr ---------------- ---------------- ---------------- ------- 0000000081200000 0000000089623000 0000000000001000 rwxu-ad 000000008120f000 0000000089624000 0000000000001000 rwxu-ad Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li
Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li
- add sm3p0, sm3p1, sm4ed and sm4ks instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in ↵Weiwei Li
zknh extension - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in ↵Weiwei Li
zknh extension - add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29crypto: move sm4_sbox from target/armWeiwei Li
- share it between target/arm and target/riscv Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li
- add xperm4 and xperm8 instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zbkc extensionWeiwei Li
- reuse partial instructions of zbc extension, update extension check for them Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add support for zbkb extensionWeiwei Li
- reuse partial instructions of zbb extension, update extension check for them - add brev8, pack, packh, packw, unzip, zip instructions Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through -cpu command line option. The default values of marchid and mipid are built with QEMU's version numbers. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220422040436.2233-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") tried to avoid adding *NULL* bootargs to device tree, but unfortunately the changes were entirely useless, due to MachineState::kernel_cmdline can't be NULL at all as the default value is given as an empty string. (see hw/core/machine.c::machine_initfn()). Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise a segfault had already been observed by dereferencing the NULL pointer. It should be worded as *empty" bootargs. Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng
At present the adding '/chosen/stdout-path' property in device tree is determined by whether a kernel command line is provided, which is wrong. It should be added unconditionally. Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-28Merge tag 'pull-target-arm-20220428' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * refactor to use tcg_constant where appropriate * Advertise support for FEAT_TTL and FEAT_BBM level 2 * smmuv3: Cache event fault record * smmuv3: Add space in guest error message * smmuv3: Advertise support for SMMUv3.2-BBML2 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJqpu4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pOQD/9G190+ntJm4Vndz0I6bCDP # svDrWwsioOJ4q5Pah6517JACkwN5sx0adMGyAeRC3Kcbz5B2141vv9hJOnJmLB1D # l6KbH8XZaftC0B8fXsPkaH6XEdBHGz6YbOZaLOTwmFqF9d18OFW4d8+CAvfldZRc # +DYeolEhoL9eLTS16BlXPxb0LajQHhbN1Xdu3t8CGh31C52ZrG4h8cus6YMEDjfA # rfBthh/2QvVFmDedIfX4QrlImCTs+bTaSkhUBmX6qakWII0QykItgQTEZ8IHEr8/ # QmG+xlkP1MmffyHU3F4inEVXpjCSzula4ycZpNVGsrTHYxLBzsTSD+EzicLHMZSt # 64tQhLxPjAzC1MEHp7bJHyQXon7REWd6u1jPRlMWTGpZqbMMchBPjFrsxK3YPdvi # a/8KIulXuX+GjzbOIHnpttIy+U0UrjTEyxjpk+Ay2iZ+U6+hA3i2ni++dzq9dYb6 # IiCl+o29r/7fNaWpG3b38kn9vpxjwAAw+qfwwSqyM+8/KMirgJ8rpEmUPei/h7fy # vqpNlVxd1+Tzb3ljCXNRriZ05xo5I9LIb+dLAig1orENS7w3SzW/GnM+S7raOwQb # u9mxNmbQJ1MhkjNC/6wzniBre6EBs31X2GIWeuiWe/js2YFPQC06b1WwIc/bYNUv # anbECOS34mtxbExFfdlxUQ== # =IPEn # -----END PGP SIGNATURE----- # gpg: Signature made Thu 28 Apr 2022 07:38:38 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm: (54 commits) hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 target/arm: Advertise support for FEAT_BBM level 2 target/arm: Advertise support for FEAT_TTL hw/arm/smmuv3: Add space in guest error message hw/arm/smmuv3: Cache event fault record target/arm: Use field names for accessing DBGWCRn target/arm: Disable cryptographic instructions when neon is disabled target/arm: Use tcg_constant for vector descriptor target/arm: Use tcg_constant for do_brk{2,3} target/arm: Use tcg_constant for predicate descriptors target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm target/arm: Use tcg_constant in SUBR target/arm: Use tcg_constant in LD1, ST1 target/arm: Use tcg_constant in WHILE target/arm: Use tcg_constant in do_clast_scalar target/arm: Use tcg_constant in {incr, wrap}_last_active target/arm: Use tcg_constant in FCPY, CPY target/arm: Use tcg_constant in SINCDEC, INCDEC target/arm: Use tcg_constant for trans_INDEX_* target/arm: Use tcg_constant in trans_CSEL ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-28hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2Peter Maydell
The Arm SMMUv3 includes an optional feature equivalent to the CPU FEAT_BBM, which permits an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the traditional 'break-before-make' dance. (This is particularly important for the SMMU, because devices performing I/O through an SMMU are less likely to be able to cope with the window in the sequence where an access results in a translation fault.) The SMMU spec explicitly notes that one of the valid ways to be a BBM level 2 compliant implementation is: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple TLB entries for an address, because the translation table level is part of the SMMUIOTLBKey, and so our IOTLB hashtable can include entries for the same address where the leaf was at different levels (i.e. both hugepage and normal page). Our TLB lookup implementation in smmu_iotlb_lookup() will always find the entry with the lowest level (i.e. it prefers the hugepage over the normal page) and ignore any others. TLB invalidation correctly removes all TLB entries matching the specified address or address range (unless the guest specifies the leaf level explicitly, in which case it gets what it asked for). So we can validly advertise support for BBML level 2. Note that we still can't yet advertise ourselves as an SMMU v3.2, because v3.2 requires support for the S2FWB feature, which we don't yet implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
2022-04-28target/arm: Advertise support for FEAT_BBM level 2Peter Maydell
The description in the Arm ARM of the requirements of FEAT_BBM is admirably clear on the guarantees it provides software, but slightly more obscure on what that means for implementations. The description of the equivalent SMMU feature in the SMMU specification (IHI0070D.b section 3.21.1) is perhaps a bit more detailed and includes some example valid implementation choices. (The SMMU version of this feature is slightly tighter than the CPU version: the CPU is permitted to raise TLB Conflict aborts in some situations that the SMMU may not. This doesn't matter for QEMU because we don't want to do TLB Conflict aborts anyway.) The informal summary of FEAT_BBM is that it is about permitting an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the 'break-before-make' dance that has traditionally been necessary. The 'break-before-make' sequence is: * replace the old translation table entry with an invalid entry * execute a DSB insn * execute a broadcast TLB invalidate insn * execute a DSB insn * write the new translation table entry * execute a DSB insn The point of this is to ensure that no TLB can simultaneously contain TLB entries for the old and the new entry, which would traditionally be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault or to use a random mishmash of values from the old and the new entry). FEAT_BBM level 2 says "for the specific case where the only thing that changed is the size of the block, the TLB is guaranteed not to do weird things even if there are multiple entries for an address", which means that software can now do: * replace old translation table entry with new entry * DSB * broadcast TLB invalidate * DSB As the SMMU spec notes, valid ways to do this include: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others * if there are multiple entries in the TLB for an address, throw them all out and do a page table walk to get a new one QEMU's page table walk implementation for Arm CPUs already meets the requirements for FEAT_BBM level 2. When we cache an entry in our TCG TLB, we do so only for the specific (non-huge) page that the address is in, and there is no way for the TLB data structure to ever have more than one TLB entry for that page. (We handle huge pages only in that we track what part of the address space is covered by huge pages so that a TLB invalidate operation for an address in a huge page results in an invalidation of the whole TLB.) We ignore the Contiguous bit in page table entries, so we don't have to do anything for the parts of FEAT_BBM that deal with changis to the Contiguous bit. FEAT_BBM level 2 also requires that the nT bit in block descriptors must be ignored; since commit 39a1fd25287f5dece5 we do this. It's therefore safe for QEMU to advertise FEAT_BBM level 2 by setting ID_AA64MMFR2_EL1.BBM to 2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
2022-04-28target/arm: Advertise support for FEAT_TTLPeter Maydell
The Arm FEAT_TTL architectural feature allows the guest to provide an optional hint in an AArch64 TLB invalidate operation about which translation table level holds the leaf entry for the address being invalidated. QEMU's TLB implementation doesn't need that hint, and we correctly ignore the (previously RES0) bits in TLB invalidate operation values that are now used for the TTL field. So we can simply advertise support for it in our 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
2022-04-28hw/arm/smmuv3: Add space in guest error messageJean-Philippe Brucker
Make the translation error message prettier by adding a missing space before the parenthesis. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220427111543.124620-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 16:13:39 +0000