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2015-09-14Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20150914' into staging target-arm queue: * fix GIC region size in xlnx-zynqmp * xlnx-zynqmp: Remove unnecessary brackets * improve A64 generated TCG code * add GPIO devices to i.MX25 and i.MX31 * more missing pieces for EL2 support # gpg: Signature made Mon 14 Sep 2015 14:51:12 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20150914: (24 commits) target-arm: Add VMPIDR_EL2 target-arm: Break out mpidr_read_val() target-arm: Add VPIDR_EL2 target-arm: Suppress EPD for S2, EL2 and EL3 translations target-arm: Suppress TBI for S2 translations target-arm: Add VTTBR_EL2 target-arm: Add VTCR_EL2 hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully i.MX: Add GPIO devices to i.MX25 SOC i.MX: Add GPIO devices to i.MX31 SOC i.MX: Add GPIO device target-arm: Use tcg_gen_extrh_i64_i32 target-arm: Recognize ROR target-arm: Eliminate unnecessary zero-extend in disas_bitfield target-arm: Recognize UXTB, UXTH, LSR, LSL target-arm: Recognize SXTB, SXTH, SXTW, ASR target-arm: Implement fcsel with movcond target-arm: Implement ccmp branchless target-arm: Use setcond and movcond for csel target-arm: Handle always condition codes within arm_test_cc ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias
Break out mpidr_read_val() to allow future sharing of the code that conditionally sets the M and U bits of MPIDR. No functional changes. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-7-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias
Stage-2 translations, EL2 and EL3 regimes don't have the EPD control. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-6-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias
Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed typo in comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefullyEdgar E. Iglesias
Handle missing CPU support for EL3 gracefully. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14i.MX: Add GPIO devices to i.MX25 SOCJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 2eb129ba8713aedfe877eaa3d8de80061d880fbb.1441828793.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14i.MX: Add GPIO devices to i.MX31 SOCJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 60b67c9a8b948159f4b4163ead86fbf701c011c6.1441828793.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14i.MX: Add GPIO deviceJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 5ea3b0021e47cf7f7d883a7edbabee44980f3df7.1441828793.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson
Usually, eliminate an operation from the translator by combining a shift with an extract. In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF, merely a non-zero value. Given that we can extract both halves of a 64-bit input in one call, this simplifies the code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-12-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Recognize RORRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-11-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson
For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) But since the range of bits for !SF are already constrained by unallocated_encoding, we'll never reference the high bits anyway. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-10-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson
These are all special case aliases of UBFM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-9-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson
These are all special case aliases of SBFM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-8-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Implement fcsel with movcondRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-7-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Implement ccmp branchlessRichard Henderson
This can allow much of a ccmp to be elided when particular flags are subsequently dead. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-6-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Use setcond and movcond for cselRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-5-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson
Handling this with TCG_COND_ALWAYS will allow these unlikely cases to be handled without special cases in the rest of the translator. The TCG optimizer ought to be able to reduce these ALWAYS conditions completely. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-4-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Introduce DisasCompareRichard Henderson
Split arm_gen_test_cc into 3 functions, so that it can be reused for non-branch TCG comparisons. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-3-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson
This is a bug fix for aarch64. At present, we have branches using the 32-bit (translate.c) versions of cpu_[NZCV]F, but we set the flags using the 64-bit (translate-a64.c) versions of cpu_[NZCV]F. From the view of the TCG code generator, these are unrelated variables. The bug is hard to see because we currently only read these variables from branches, and upon reaching a branch TCG will first spill live variables and then reload the arguments of the branch. Since the 32-bit versions were never live until reaching the branch, we'd re-read the data that had just been spilled from the 64-bit versions. There is currently no such problem with the cpu_exclusive_* variables, but there's no point in tempting fate. Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1441909103-24666-2-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14xlnx-zynqmp: Remove unnecessary brackets around error messagesAlistair Francis
The errp and err variable have unnecessary brackets around them, so remove the brackets. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 9900393572b63f2ec3d68785ca98193d81e0ac71.1441758563.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14arm: xlnx-zynqmp: Fix up GIC region sizeNathan Rossi
The GIC in ZynqMP cover a 64K address space, however the actual registers are decoded within a 4K address space and mirrored at the 4K boundaries. This change fixes the defined size for these regions as it was set to 0x4000/16K incorrectly. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441719672-25296-1-git-send-email-nathan@nathanrossi.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-14Merge remote-tracking branch 'remotes/aurel/tags/pull-sh4-next-20150913' ↵Peter Maydell
into staging sh4-next: - TCG optimizations - fix initramfs endianness issue # gpg: Signature made Sun 13 Sep 2015 22:16:12 BST using RSA key ID 1DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-sh4-next-20150913: sh4: Fix initramfs initialization for endiannes-mismatched targets target-sh4: improve shad instruction target-sh4: improve shld instruction target-sh4: improve cmp/str instruction target-sh4: use deposit in swap.b instruction target-sh4: add flags markups for FP helpers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-13sh4: Fix initramfs initialization for endiannes-mismatched targetsGuenter Roeck
If host and target endianness does not match, loding an initramfs does not work. Fix by writing boot parameters with appropriate endianness conversion. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-13target-sh4: improve shad instructionAurelien Jarno
The SH4 shad instruction can shift in both direction, depending on the sign of the shift. This is currently implemented using branches, which is not really efficient and prevents the optimizer to do its job. In practice it is often used with a constant loaded in a register just before. Simplify the implementation by computing both the value shifted to the left and to the right, and then selecting the correct one with a movcond. As with a negative value the shift amount can go up to 32 which is undefined, we shift the value in two steps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-13target-sh4: improve shld instructionAurelien Jarno
The SH4 shld instruction can shift in both direction, depending on the sign of the shift. This is currently implemented using branches, which is not really efficient and prevents the optimizer to do its job. In practice it is often used with a constant loaded in a register just before. Simplify the implementation by computing both the value shifted to the left and to the right, and then selecting the correct one with a movcond. As with a negative value the shift amount can go up to 32 which is undefined, we shift the value in two steps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-13target-sh4: improve cmp/str instructionAurelien Jarno
Instead of testing bytes one by one, we can use the following trick from https://graphics.stanford.edu/~seander/bithacks.html: haszero(v) = (v - 0x01010101) & ~v & 0x80808080 The subexpression v - 0x01010101, evaluates to a high bit set in any byte whenever the corresponding byte in v is zero or greater than 0x80. The sub-expression ~v & 0x80808080 evaluates to high bits set in bytes where the byte of v doesn't have its high bit set (so the byte was less than 0x80). Finally, by ANDing these two sub-expressions the result is the high bits set where the bytes in v were zero, since the high bits set due to a value greater than 0x80 in the first sub-expression are masked off by the second. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-13target-sh4: use deposit in swap.b instructionAurelien Jarno
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-13target-sh4: add flags markups for FP helpersAurelien Jarno
Most floating point helpers can trigger an exception, but don't change the globals. Mark these helpers as TCG_CALL_NO_WG. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2015-09-11Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150911' into stagingPeter Maydell
queued tcg related patches # gpg: Signature made Fri 11 Sep 2015 16:17:00 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20150911: cpu-exec: introduce loop exit with restore function softmmu: remove now unused functions softmmu: add helper function to pass through retaddr tlb: Add "ifetch" argument to cpu_mmu_index() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-11scripts/qemu-gdb: Add brief comment describing usagePeter Maydell
Add a brief comment describing how to use the debug support from GDB. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1439574392-4403-5-git-send-email-peter.maydell@linaro.org
2015-09-11scripts/qemu-gdb: Silently pass through SIGUSR1Peter Maydell
SIGUSR1 is QEMU's IPI signal, and it gets sent a lot, so is best silently passed through to the guest without stopping. Make qemu-gdb.py do this bit of configuration for the user. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1439574392-4403-4-git-send-email-peter.maydell@linaro.org
2015-09-11scripts/qemu-gdb: Split CoroutineCommand into its own filePeter Maydell
Split the implementation of CoroutineCommand into its own file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1439574392-4403-3-git-send-email-peter.maydell@linaro.org
2015-09-11scripts/qemu-gdb: Split MtreeCommand into its own modulePeter Maydell
As we add more commands to our Python gdb debugging support, it's going to get unwieldy to have everything in a single file. Split the implementation of the 'mtree' command from qemu-gdb.py into its own module. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1439574392-4403-2-git-send-email-peter.maydell@linaro.org
2015-09-11cpu-exec: introduce loop exit with restore functionPavel Dovgalyuk
This patch introduces loop exit function, which also restores guest CPU state according to the value of host program counter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20150710095702.13280.97477.stgit@PASHA-ISP> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11softmmu: remove now unused functionsPavel Dovgalyuk
Now that the cpu_ld/st_* function directly call helper_ret_ld/st, we can drop the old helper_ld/st functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20150710095656.13280.7085.stgit@PASHA-ISP> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11softmmu: add helper function to pass through retaddrPavel Dovgalyuk
This patch introduces several helpers to pass return address which points to the TB. Correct return address allows correct restoring of the guest PC and icount. These functions should be used when helpers embedded into TB invoke memory operations. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Message-Id: <20150710095650.13280.32255.stgit@PASHA-ISP> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11Merge remote-tracking branch ↵Peter Maydell
'remotes/mjt/tags/pull-trivial-patches-2015-09-11' into staging trivial patches for 2015-09-11 # gpg: Signature made Fri 11 Sep 2015 12:02:43 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2015-09-11: (26 commits) virtio-vga: enable for i386 hw/arm/spitz: Remove meaningless blank Property hw/gpio/zaurus: Remove meaningless blank Property hw/virtio/virtio-pci: Remove meaningless blank Property hw/s390x/s390-virtio-bus: Remove meaningless blank Property typofixes - v4 qapi-schema: remove legacy<> from doc disas/microblaze: Remove unused code help: dd missing newline Target-ppc: Remove unnecessary variable baum: Fix build with debugging enabled linux-user: Fix warnings caused by missing 'static' attribute opts: produce valid command line in qemu_opts_print docs: fix a qga/qapi-schema.json comment trivial: remove trailing newline from error_report maint: avoid useless "if (foo) free(foo)" pattern maint: avoid useless "if (foo) free(foo)" pattern maint: remove unused include for strings.h maint: remove unused include for signal.h maint: remove unused include for dirent.h ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-11virtio-vga: enable for i386Gerd Hoffmann
This one just syncs x86_64 and i386. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: qemu-trivial@nongnu.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11hw/arm/spitz: Remove meaningless blank PropertyShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11hw/gpio/zaurus: Remove meaningless blank PropertyShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11hw/virtio/virtio-pci: Remove meaningless blank PropertyShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11hw/s390x/s390-virtio-bus: Remove meaningless blank PropertyShannon Zhao
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11typofixes - v4Veres Lajos
Signed-off-by: Veres Lajos <vlajos@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11qapi-schema: remove legacy<> from docMarc-André Lureau
The legacy<> type is no longer used since 7ce7ffe02. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11disas/microblaze: Remove unused codeStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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