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2018-08-20hw/dma/pl080: Provide device reset functionPeter Maydell
The PL080/PL081 model is missing a reset function; implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Don't use CPU address space for DMA accessesPeter Maydell
Currently our PL080/PL081 model uses a combination of the CPU's address space (via cpu_physical_memory_{read,write}()) and the system address space for performing DMA accesses. For the PL081s in the MPS FPGA images, their DMA accesses must go via Master Security Controllers. Switch the PL080/PL081 model to take a MemoryRegion property which defines its downstream for making DMA accesses. Since the PL08x are only used in two board models, we make provision of the 'downstream' link mandatory and convert both users at once, rather than having it be optional with a default to the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Support all three interrupt linesPeter Maydell
The PL080 and PL081 have three outgoing interrupt lines: * DMACINTERR signals DMA errors * DMACINTTC is the DMA count interrupt * DMACINTR is a combined interrupt, the logical OR of the other two We currently only implement DMACINTR, because that's all the realview and versatile boards needed, but the instances of the PL081 in the MPS2 firmware images use all three interrupt lines. Implement the missing DMACINTERR and DMACINTTC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Allow use as embedded-struct devicePeter Maydell
Create a new include file for the pl081's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20nvic: Expose NMI linePeter Maydell
On real v7M hardware, the NMI line is an externally visible signal that an SoC or board can toggle to assert an NMI. Expose it in our QEMU NVIC and armv7m container objects so that a board model can wire it up if it needs to. In particular, the MPS2 watchdog is wired to NMI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog modulePeter Maydell
The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/timer/m48t59: Move away from old_mmio accessorsPeter Maydell
Move the m48t59 device away from using old_mmio MemoryRegionOps accessors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20180802180602.22047-1-peter.maydell@linaro.org
2018-08-20hw/misc: Remove mmio_interface devicePeter Maydell
The mmio_interface device was a purely internal artifact of the implementation of the memory subsystem's request_ptr APIs. Now that we have removed those APIs, we can remove the mmio_interface device too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-id: 20180817114619.22354-4-peter.maydell@linaro.org
2018-08-20memory: Remove MMIO request_ptr APIsPeter Maydell
Remove the obsolete MMIO request_ptr APIs; they have no users now. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-id: 20180817114619.22354-3-peter.maydell@linaro.org
2018-08-20hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr codePeter Maydell
We now support direct execution from MMIO regions in the core memory subsystem. This means that we don't need to have device-specific support for it, and we can remove the request_ptr handling from the Xilinx SPIPS device. (It was broken anyway due to race conditions, and disabled by default.) This device is the only in-tree user of this API. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-id: 20180817114619.22354-2-peter.maydell@linaro.org
2018-08-20sdhci: add i.MX SD Stable Clock bitHans-Erik Floryd
Add the ESDHC PRSSTAT_SDSTB bit, using the value of SDHC_CLOCK_INT_STABLE. Freescale recommends checking this bit when changing clock frequency. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534507843-4251-1-git-send-email-hans-erik.floryd@rt-labs.com [PMM: fixed indentation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/arm/virt: Add virt-3.1 machine typeAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20target/arm: Implement AArch32 ERET instructionPeter Maydell
ARMv7VE introduced the ERET instruction, which is necessary to return from an exception taken to Hyp mode. Implement this. In A32 encoding it is a completely new encoding; in T32 it is an adjustment of the behaviour of the existing "SUBS PC, LR, #<imm8>" instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-10-peter.maydell@linaro.org
2018-08-20target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)Peter Maydell
The MSR (banked) and MRS (banked) instructions allow accesses to ELR_Hyp from either Monitor or Hyp mode. Our translate time check was overly strict and only permitted access from Monitor mode. The runtime check we do in msr_mrs_banked_exc_checks() had the correct code in it, but never got there because of the earlier "currmode == tgtmode" check. Special case ELR_Hyp. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-9-peter.maydell@linaro.org
2018-08-20target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2Peter Maydell
The AArch32 HSR is the equivalent of AArch64 ESR_EL2; we can implement it by marking our existing ESR_EL2 regdef as STATE_BOTH. It also needs to be "RES0 from EL3 if EL2 not implemented", so add the missing stanza to el3_no_el2_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-8-peter.maydell@linaro.org
2018-08-20target/arm: Implement AArch32 Hyp FARsPeter Maydell
The AArch32 virtualization extensions support these fault address registers: * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) Implement the accessors for these. This fixes in passing a bug where we weren't implementing the "RES0 from EL3 if EL2 not implemented" behaviour for AArch64 FAR_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-7-peter.maydell@linaro.org
2018-08-20target/arm: Implement AArch32 HVBARPeter Maydell
Implement the AArch32 HVBAR register; we can do this just by making the existing VBAR_EL2 regdefs be STATE_BOTH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-5-peter.maydell@linaro.org
2018-08-20target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefsPeter Maydell
ARMCPRegInfo structs will default to .cp = 15 if they are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32 (because a coprocessor number of 0 is valid for AArch32). We forgot to explicitly set .cp = 15 for the HMAIR1 and HAMAIR1 regdefs, which meant they would UNDEF when the guest tried to access them under cp15. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-3-peter.maydell@linaro.org
2018-08-20target/arm: Correct typo in HAMAIR1 regdef namePeter Maydell
We implement the HAMAIR1 register as RAZ/WI; we had a typo in the regdef, though, and were incorrectly naming it HMAIR1 (which is a different register which we also implement as RAZ/WI). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-2-peter.maydell@linaro.org
2018-08-20imx_serial: Generate interrupt on receive data ready if enabledHans-Erik Floryd
Generate an interrupt if USR2_RDR and UCR4_DREN are both set. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/intc/arm_gicv3_its: downgrade error_report to warn_report in ↵Jia He
kvm_arm_its_reset In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu output log with: if [ -z "$(echo "$errors" | grep -vi warning)" ]; then Thus without the warning prefix, all of the test fail. Since it is not unrecoverable error in kvm_arm_its_reset for current implementation, downgrading the report from error to warn makes sense. Signed-off-by: Jia He <jia.he@hxt-semitech.com> Message-id: 1531969910-32843-1-git-send-email-jia.he@hxt-semitech.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20docs/generic-loader: mention U-Boot and Intel HEX executable formatsStefan Hajnoczi
The generic loader device supports the U-Boot and Intel HEX executable formats in addition to the document raw and ELF formats. Reword the documentation to include these formats and explain how various options depend on the executable format. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20180816145554.9814-1-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20target/arm: Fix crash on conditional instruction in an IT blockRoman Kapl
If an instruction is conditional (like CBZ) and it is executed conditionally (using the ITx instruction), a jump to an undefined label is generated, and QEMU crashes. CBZ in IT block is an UNPREDICTABLE behavior, but we should not crash. Honouring the condition code is allowed by the spec in this case (constrained unpredictable, ARMv8, section K1.1.7), and matches what we do for other "UNPREDICTABLE inside an IT block" instructions. Fix the 'skip on condition' code to create a new label only if it does not already exist. Previously multiple labels were created, but only the last one of them was set. Signed-off-by: Roman Kapl <rka@sysgo.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180816120533.6587-1-rka@sysgo.com [PMM: fixed ^ 1 being applied to wrong argument, fixed typo] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2018-08-17 * Allow machine classes to specify if boot device suffixes should be ignored by get_boot_devices_list() * Tiny coding style fixup # gpg: Signature made Fri 17 Aug 2018 19:29:22 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: fw_cfg: ignore suffixes in the bootdevice list dependent on machine class sysbus: always allow explicit_ofw_unit_address() to override address generation machine: Fix coding style at machine_run_board_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-17Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20180817.0' ↵Peter Maydell
into staging VFIO update 2018-08-17 - Enhance balloon inhibitor for multiple users and use around vfio device assignment (Alex Williamson) # gpg: Signature made Fri 17 Aug 2018 17:43:37 BST # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-update-20180817.0: vfio/ccw/pci: Allow devices to opt-in for ballooning vfio: Inhibit ballooning based on group attachment to a container kvm: Use inhibit to prevent ballooning without synchronous mmu balloon: Allow multiple inhibit users Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-17vfio/ccw/pci: Allow devices to opt-in for ballooningAlex Williamson
If a vfio assigned device makes use of a physical IOMMU, then memory ballooning is necessarily inhibited due to the page pinning, lack of page level granularity at the IOMMU, and sufficient notifiers to both remove the page on balloon inflation and add it back on deflation. However, not all devices are backed by a physical IOMMU. In the case of mediated devices, if a vendor driver is well synchronized with the guest driver, such that only pages actively used by the guest driver are pinned by the host mdev vendor driver, then there should be no overlap between pages available for the balloon driver and pages actively in use by the device. Under these conditions, ballooning should be safe. vfio-ccw devices are always mediated devices and always operate under the constraints above. Therefore we can consider all vfio-ccw devices as balloon compatible. The situation is far from straightforward with vfio-pci. These devices can be physical devices with physical IOMMU backing or mediated devices where it is unknown whether a physical IOMMU is in use or whether the vendor driver is well synchronized to the working set of the guest driver. The safest approach is therefore to assume all vfio-pci devices are incompatible with ballooning, but allow user opt-in should they have further insight into mediated devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17vfio: Inhibit ballooning based on group attachment to a containerAlex Williamson
We use a VFIOContainer to associate an AddressSpace to one or more VFIOGroups. The VFIOContainer represents the DMA context for that AdressSpace for those VFIOGroups and is synchronized to changes in that AddressSpace via a MemoryListener. For IOMMU backed devices, maintaining the DMA context for a VFIOGroup generally involves pinning a host virtual address in order to create a stable host physical address and then mapping a translation from the associated guest physical address to that host physical address into the IOMMU. While the above maintains the VFIOContainer synchronized to the QEMU memory API of the VM, memory ballooning occurs outside of that API. Inflating the memory balloon (ie. cooperatively capturing pages from the guest for use by the host) simply uses MADV_DONTNEED to "zap" pages from QEMU's host virtual address space. The page pinning and IOMMU mapping above remains in place, negating the host's ability to reuse the page, but the host virtual to host physical mapping of the page is invalidated outside of QEMU's memory API. When the balloon is later deflated, attempting to cooperatively return pages to the guest, the page is simply freed by the guest balloon driver, allowing it to be used in the guest and incurring a page fault when that occurs. The page fault maps a new host physical page backing the existing host virtual address, meanwhile the VFIOContainer still maintains the translation to the original host physical address. At this point the guest vCPU and any assigned devices will map different host physical addresses to the same guest physical address. Badness. The IOMMU typically does not have page level granularity with which it can track this mapping without also incurring inefficiencies in using page size mappings throughout. MMU notifiers in the host kernel also provide indicators for invalidating the mapping on balloon inflation, not for updating the mapping when the balloon is deflated. For these reasons we assume a default behavior that the mapping of each VFIOGroup into the VFIOContainer is incompatible with memory ballooning and increment the balloon inhibitor to match the attached VFIOGroups. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson
Remove KVM specific tests in balloon_page(), instead marking ballooning as inhibited without KVM_CAP_SYNC_MMU support. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17balloon: Allow multiple inhibit usersAlex Williamson
A simple true/false internal state does not allow multiple users. Fix this within the existing interface by converting to a counter, so long as the counter is elevated, ballooning is inhibited. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell
into staging x86 queue, 2018-08-16 Bug fix: * Some guests may crash when using "-cpu host" due to TOPOEXT, disable it by default Features: * PV_SEND_IPI feature bit * Icelake-{Server,Client} CPU models * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES Documentation: * docs/qemu-cpu-models.texi # gpg: Signature made Fri 17 Aug 2018 02:33:09 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Disable TOPOEXT by default on "-cpu host" target-i386: adds PV_SEND_IPI CPUID feature bit i386: Add new CPU model Icelake-{Server,Client} i386: Add CPUID bit for WBNOINVD i386: Add CPUID bit for PCONFIG i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES docs: add guidance on configuring CPU models for x86 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16fw_cfg: ignore suffixes in the bootdevice list dependent on machine classMark Cave-Ayland
For the older machines (such as Mac and SPARC) the DT nodes representing bootdevices for disk nodes are irregular for mainly historical reasons. Since the majority of bootdevice nodes for these machines either do not have a separate disk node or require different (custom) names then it is much easier for processing to just disable all suffixes for a particular machine. Introduce a new ignore_boot_device_suffixes MachineClass property to control bootdevice suffix generation, defaulting to false in order to preserve compatibility. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20180810124027.10698-1-mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16sysbus: always allow explicit_ofw_unit_address() to override address generationMark Cave-Ayland
Some SysBusDevices either use sysbus_init_mmio() without sysbus_mmio_map() or the first MMIO memory region doesn't represent the bus address, causing a firmware device path with an invalid address to be generated. SysBusDeviceClass does provide a virtual explicit_ofw_unit_address() method that can be used to override this process, but it was originally intended only as as a fallback option meaning that any existing MMIO memory regions still take priority whilst determining the firmware device address. There is currently only one user of explicit_ofw_unit_address() and that is the PCI expander bridge (PXB) device which has no MMIO/PIO resources defined. This enables us to allow explicit_ofw_unit_address() to take priority without affecting backwards compatibility, allowing the address to be customised as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20180805112850.26063-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16machine: Fix coding style at machine_run_board_init()Dou Liyang
Commit 7747abf11487 ("hw/machine: Remove the Zero check of nb_numa_nodes for numa_complete_configuration()") removed the curly brackets. Re-add them. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <20180710105129.23296-1-douly.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [ehabkost: rewrote commit message] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' ↵Peter Maydell
into staging MIPS queue Aug 16, 2018 # gpg: Signature made Thu 16 Aug 2018 18:19:36 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: qemu-doc: Amend MIPS-related items linux-user: Add preprocessor availability control to some syscalls linux-user: Update MIPS syscall numbers up to kernel 4.18 headers elf: Add ELF flags for MIPS machine variants elf: Remove duplicate preprocessor constant definition target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 target/mips: Don't update BadVAddr register in Debug Mode target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add CP0 BadInstrX register target/mips: Update some CP0 registers bit definitions target/mips: Fix two instances of shadow variables target/mips: Mark switch fallthroughs with interpretable comments target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Avoid case statements formulated by ranges - part 1 MAINTAINERS: Update target/mips maintainer's email addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16qemu-doc: Amend MIPS-related itemsAleksandar Markovic
Amend MIPS-related items in qemu-doc.texi Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Add preprocessor availability control to some syscallsAleksandar Rikalo
Add ability to target platforms to individually include user-mode support for system calls from "stat" group of system calls. This change is related to new nanoMIPS platform in the sense that it supports a different set of "stat" system calls than any other target. nanoMIPS does not support structures stat and stat64 at all. Also, support for certain number of other system calls is dropped in nanoMIPS (those are most of the time obsoleted system calls). Without this patch, build for nanoMIPS would fail. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Update MIPS syscall numbers up to kernel 4.18 headersAleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 9 new syscall numbers, the last being NR_io_pgetevents. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Add ELF flags for MIPS machine variantsAleksandar Markovic
Add MIPS machine variants ELF flags so that the emulation behavior can be adjusted if needed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Remove duplicate preprocessor constant definitionAleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH. The duplicate was introduced in commit 45506bdd. It placed the constant EF_MIPS_ARCH in a better place, however it did not remove the original. This patch removes the original occurrence. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is set. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Implement CP0 Config1.WR bit functionalityStefan Markovic
Add testing Config1.WR bit into watch exception handling logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Add CP0 BadInstrX registerStefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Update some CP0 registers bit definitionsAleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3, Config4, and Config5 bit definitions. Some of these bits will be utilized by upcoming nanoMIPS changes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Fix two instances of shadow variablesAleksandar Markovic
Fix two instances of shadow variables. This cleans up entire file translate.c from shadow variables. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Mark switch fallthroughs with interpretable commentsAleksandar Markovic
Mark switch fallthroughs with comments, in cases fallthroughs are intentional. The comments "/* fall through */" are interpreted by compilers and other tools, and they will not issue warnings in such cases. For gcc, the warning is turnend on by -Wimplicit-fallthrough. With this patch, there will be no such warnings in target/mips directory. If such warning appears in future, it should be checked if it is intentional, and, if yes, marked with a comment similar to those from this patch. The comment must be just before next "case", otherwise gcc won't understand it. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 2Aleksandar Rikalo
Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 1Aleksandar Markovic
Remove "range style" case statements to make code analysis easier. This is needed also for some upcoming nanoMIPS-related refactorings. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16MAINTAINERS: Update target/mips maintainer's email addressesAleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the MAINTAINERS file. Also, add corresponding items in the .mailmap file. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16i386: Disable TOPOEXT by default on "-cpu host"Eduardo Habkost
Enabling TOPOEXT is always allowed, but it can't be enabled blindly by "-cpu host" because it may make guests crash if the rest of the cache topology information isn't provided or isn't consistent. This addresses the bug reported at: https://bugzilla.redhat.com/show_bug.cgi?id=1613277 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180809221852.15285-1-ehabkost@redhat.com> Tested-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-23 18:58:36 +0000