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2018-07-03target/ppc: Use atomic cmpxchg for STQCXRichard Henderson
When running in a parallel context, we must use a helper in order to perform the 128-bit atomic operation. When running in a serial context, do the compare before the store. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic store for STQRichard Henderson
Section 1.4 of the Power ISA v3.0B states that this insn is single-copy atomic. As we cannot (yet) issue 128-bit stores within TCG, use the generic helpers provided. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Use atomic load for LQ and LQARXRichard Henderson
Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03target/ppc: Add do_unaligned_access hookRichard Henderson
This allows faults from MO_ALIGN to have the same effect as from gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/pnv: fix pnv_core_realize() error handlingCédric Le Goater
commit d35aefa9ae15 ("ppc/pnv: introduce a new intc_create() operation to the chip model") changed the object link in the pnv_core_realize() routine but a return was forgotten in case of error, which can lead to more problems afterwards (segv) Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/xics: rework the ICS classes inheritance treeCédric Le Goater
With the previous changes, we can now let the ICS_KVM class inherit directly from ICS_BASE class and not from the intermediate ICS_SIMPLE. It makes the class hierarchy much cleaner. What is left in the top classes is the low level interface to access the KVM XICS device in ICS_KVM and the XICS emulating handlers in ICS_SIMPLE. This should not break migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/xics: move the vmstate structures under the ics-base classCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppx/xics: introduce a parent_reset in ICSStateClassCédric Le Goater
Just like for the realize handlers, this makes possible to move the common ICSState code of the reset handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/xics: move the instance_init handler under the ics-base classCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/xics: introduce a parent_realize in ICSStateClassCédric Le Goater
This makes possible to move the common ICSState code of the realize handlers in the ics-base class. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03ppc/xics: introduce ICP DeviceRealize and DeviceReset handlersCédric Le Goater
This changes the ICP realize and reset handlers in DeviceRealize and DeviceReset handlers. parent handlers are now called from the inheriting classes which is a cleaner object pattern. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03sam460ex: Fix sam460ex device tree when booting the Linux kernelGuenter Roeck
sam460ex (or at least this emulation) does not support the "ibm,cpm" power management. As a result, Linux crashes when trying to access it. Remove its device tree node. Also, if/when we boot the Linux kernel directly, serial port clock frequencies in the device tree file will be unset, and serial port initialization will fail. Add valid frequency values to the serial ports to be able to use it. Also set valid values for the other clock nodes otherwise set by u-boot. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03mac_newworld: always enable disable_direct_reg3_writes for ADB machinesMark Cave-Ayland
Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a workaround for MacOS 9 incorrectly setting the mouse address during boot of PMU machines. Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte ordering" this can still sometimes happen with the CUDA mac99 machine, so let's enable this workaround for all New World machines using ADB for now. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03mac_dbdma: only dump commands for debug enabled channelsMark Cave-Ayland
This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the DBDMA command execution debug output. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-02nbd/client: Add x-dirty-bitmap to query bitmap from serverEric Blake
In order to test that the NBD server is properly advertising dirty bitmaps, we need a bare minimum client that can request and read the context. Since feature freeze for 3.0 is imminent, this is the smallest workable patch, which replaces the qemu block status report with the results of the NBD server's dirty bitmap (making it very easy to use 'qemu-img map --output=json' to learn where the dirty portions are). Note that the NBD protocol defines a dirty section with the same bit but opposite sense that normal "base:allocation" uses to report an allocated section; so in qemu-img map output, "data":true corresponds to clean, "data":false corresponds to dirty. A more complete solution that allows dirty bitmaps to be queried at the same time as normal block status will be required before this addition can lose the x- prefix. Until then, the fact that this replaces normal status with dirty status means actions like 'qemu-img convert' will likely misbehave due to treating dirty regions of the file as if they are unallocated. The next patch adds an iotest to exercise this new code. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180702191458.28741-2-eblake@redhat.com>
2018-07-02iotests: add 222 to test basic fleecingJohn Snow
Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20180702194630.9360-3-jsnow@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com>
2018-07-02blockdev: enable non-root nodes for backup sourceVladimir Sementsov-Ogievskiy
This is needed to implement the image-fleecing workflow where we create a temporary node backed by an active node, then start backupdev-backup sync=none from the active node to the temp node. In this case, the active node is now a root node AND a backing node, so it no longer qualifies as a root node, so we loosen the restriction on which nodes can be considered as the source for a backup. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20180702194630.9360-2-jsnow@redhat.com> Signed-off-by: Eric Blake <eblake@redhat.com>
2018-07-02iscsi: Avoid potential for get_status overflowEric Blake
Detected by Coverity: Multiplying two 32-bit int and assigning the result to a 64-bit number is a risk of overflow. Prior to the conversion to byte-based interfaces, the block layer took care of ensuring that a status request never exceeded 2G in the driver; but after that conversion, the block layer expects drivers to deal with any size request (the driver can always truncate the request size back down, as long as it makes progress). So, in the off-chance that someone makes a large request, we are at the mercy of whether iscsi_get_lba_status_task() will cap things to at most INT_MAX / iscsilun->block_size when it populates lbasd->num_blocks; since I could not easily audit that, it's better to be safe than sorry by just forcing a 64-bit multiply. Fixes: 92809c36 CC: qemu-stable@nongnu.org Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180508212718.1482663-1-eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-07-02nbd/server: Fix dirty bitmap logic regressionEric Blake
In my hurry to fix a build failure, I introduced a logic bug. The assertion conditional is backwards, meaning that qemu will now abort instead of reporting dirty bitmap status. The bug can only be tickled by an NBD client using an exported dirty bitmap (which is still an experimental QMP command), so it's not the end of the world for supported usage (and neither 'make check' nor qemu-iotests fails); but it also shows that we really want qemu-io support for reading dirty bitmaps if only so that I can add iotests coverage to prevent future brown-bag-of-shame events like this one. Fixes: 45eb6fb6 Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180622153509.375130-1-eblake@redhat.com>
2018-07-02linux-user: update do_setsockopt()Laurent Vivier
add IPV6_MULTICAST_HOPS and IPV6_MULTICAST_LOOP that need 32bit value conversion Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180627212152.26525-3-laurent@vivier.eu>
2018-07-02linux-user: add netlink CARRIER_UP_COUNT/CARRIER_DOWN_COUNTLaurent Vivier
Error is reported with libuv test suite: not ok 311 - udp_multicast_interface6 # exit code 134 # Output from process `udp_multicast_interface6`: # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180627212152.26525-2-laurent@vivier.eu>
2018-07-02qemu-binfmt-conf.sh: allow to provide a suffix to the interpreter nameLaurent Vivier
some distros provide a qemu-CPU-static binary beside the qemu-CPU one. This change allows to use it by providing "--qemu-suffix -static" to the script. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180627205317.10343-4-laurent@vivier.eu>
2018-07-02qemu-binfmt-conf.sh: add persistent (F) flagsLaurent Vivier
Since kernel commit 948b701a607f (binfmt_misc: add persistent opened binary handler for containers) kernel allows to load the interpreter at the configuration time. In case of chroot, it allows to have the interpreter in the host root filesystem and not to copy it to the chroot filesystem. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180627205317.10343-3-laurent@vivier.eu>
2018-07-02qemu-binfmt-conf.sh: cleanup --credentialLaurent Vivier
move credential value to its own variable to be able to manage more flags Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180627205317.10343-2-laurent@vivier.eu>
2018-07-02Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* IEC units series (Philippe) * Hyper-V PV TLB flush (Vitaly) * git archive detection (Daniel) * host serial passthrough fix (David) * NPT support for SVM emulation (Jan) * x86 "info mem" and "info tlb" fix (Doug) # gpg: Signature made Mon 02 Jul 2018 16:18:21 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (50 commits) tcg: simplify !CONFIG_TCG handling of tb_invalidate_* i386/monitor.c: make addresses canonical for "info mem" and "info tlb" target-i386: Add NPT support serial: Open non-block bsd-user: Use the IEC binary prefix definitions linux-user: Use the IEC binary prefix definitions tests/crypto: Use the IEC binary prefix definitions vl: Use the IEC binary prefix definitions monitor: Use the IEC binary prefix definitions cutils: Do not include "qemu/units.h" directly hw/rdma: Use the IEC binary prefix definitions hw/virtio: Use the IEC binary prefix definitions hw/vfio: Use the IEC binary prefix definitions hw/sd: Use the IEC binary prefix definitions hw/usb: Use the IEC binary prefix definitions hw/net: Use the IEC binary prefix definitions hw/i386: Use the IEC binary prefix definitions hw/ppc: Use the IEC binary prefix definitions hw/mips: Use the IEC binary prefix definitions hw/mips/r4k: Constify params_size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180702' into stagingPeter Maydell
Assorted tlb and tb caching fixes # gpg: Signature made Mon 02 Jul 2018 17:03:07 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20180702: cpu: Assert asidx_from_attrs return value in range accel/tcg: Avoid caching overwritten tlb entries accel/tcg: Don't treat invalid TLB entries as needing recheck accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code() tcg: Define and use new tlb_hit() and tlb_hit_page() functions translate-all: fix locking of TBs whose two pages share the same physical page Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/seabios-1.11.2-20180702-pull-request' into staging seabios: update to release 1.11.2, add/update configuration. vgabios: remove (old unused lgpl'ed vgabios). ramfb,bochs-display: use new vgabios roms. # gpg: Signature made Mon 02 Jul 2018 16:42:06 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/seabios-1.11.2-20180702-pull-request: ramfb: enable vgabios bochs-display: enable vgabios seabios: update bios and vgabios binaries vgabios: remove submodule and build rules. seabios: enable ide dma seabios: add vga configs for bochs-display and ramfb seabios: update submodule to release 1.11.2 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-02ramfb: enable vgabiosGerd Hoffmann
Add vgabios binary to fw_cfg vgaroms. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02bochs-display: enable vgabiosGerd Hoffmann
Add vgabios binary to pci rom bar. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02seabios: update bios and vgabios binariesGerd Hoffmann
Adds two new vgabios binaries, for ramfb and bochs-display. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02vgabios: remove submodule and build rules.Gerd Hoffmann
It's the old, lgpl vgabios implementation. Was left in as fallback when we switched to seavgabios, so we could easily switch back in case we see regressions. It's unused since years now, reportedly doesn't even build, and lacks support for recently (and not so recently) added display devices. Zap it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02seabios: enable ide dmaGerd Hoffmann
QNX reportedly requires this to boot. Should also speed up booting other guests. Note: Upstream seabios defaults this to 'n' to due to known problems on physical hardware (qemu not affected), and wouldn't flip the default to 'y'. So we adjust our local build config accordingly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02seabios: add vga configs for bochs-display and ramfbGerd Hoffmann
Both bochs-display and ramfb are devices with a simple framebuffer and no vga emulation or text mode. seavgabios has support for text mode emulation (at vgabios call level), we are using that to provide some vga compatibility support for these devices. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02seabios: update submodule to release 1.11.2Gerd Hoffmann
git shortlog rel-1.11.1..rel-1.11.2 ----------------------------------- Gerd Hoffmann (11): optionrom: enable non-vga display devices cbvga: factor out cbvga_setup_modes() qemu: add bochs-display support cbvga_setup_modes: use real mode number instead of 0x140 cbvga_list_modes: don't list current mode twice cbvga_set_mode: disable clearmem in windows x86 emulator. bochs_display_setup: return error on failure pmm: use tmp zone on oom vgasrc: add allocate_pmm() qemu: add qemu ramfb support cbvga_set_mode: refine clear display logic Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-07-02cpu: Assert asidx_from_attrs return value in rangeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson
The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- v2: - Change VMState version.
2018-07-03target/openrisc: Stub out handle_mmu_fault for softmmuRichard Henderson
This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson
The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix tlb flushing in mtsprRichard Henderson
The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Reduce tlb to a single dimensionRichard Henderson
While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Merge mmu_helper.c into mmu.cRichard Henderson
With tlb_fill in mmu.c, we can simplify things further. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson
There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson
There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson
Rather than pass base+offset to the helper, pass the full index. In most cases the base is r0 and optimization yields a constant. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson
A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Split out is_userRichard Henderson
This allows us to limit the amount of ifdefs and isolate the test for usermode. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Link more translation blocksRichard Henderson
Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson
We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson
No need to use the interrupt mechanisms when we can simply exit the tb directly. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
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