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2016-06-14hw/misc: QOM'ify arm_l2x0.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-9-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify zaurus.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-8-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify pl061.cxiaoqiang zhao
* Merge the pl061_initfn into pl061_init * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-7-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/gpio: QOM'ify omap_gpio.cxiaoqiang zhao
* Split the old SysBus init into an instance_init and DeviceClass::realize function * Drop the SysBus init function Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-6-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify versatile_i2c.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-5-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify omap_i2c.cxiaoqiang zhao
* Split the omap_i2c_init into an instance_init and realize function * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-4-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify exynos4210_i2c.cxiaoqiang zhao
* Rename the exynos4210_i2c_realize to exynos4210_i2c_init * Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-3-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/i2c: QOM'ify bitbang_i2c.cxiaoqiang zhao
Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465815255-21776-2-git-send-email-zxq_yx_007@163.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: create the 2.7 machine typeAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1465746713-30414-5-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: introduce DEFINE_VIRT_MACHINE_AS_LATESTAndrew Jones
Create two variants of DEFINE_VIRT_MACHINE. One, just called DEFINE_VIRT_MACHINE, that does not set properties that only the latest machine type should have, and another that does. This will hopefully reduce potential for errors when adding new versions. Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 1465746713-30414-4-git-send-email-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: introduce DEFINE_VIRT_MACHINEAndrew Jones
Use DEFINE_VIRT_MACHINE to generate versioned machine type info. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465746713-30414-3-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: separate versioned type-init codeAndrew Jones
Rename machvirt_info (which is specifically for 2.6 TypeInfo) to machvirt_2_6_info, and separate the type registration of the abstract machine type from the versioned type. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465746713-30414-2-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14target-arm: Fix reset and migration of TTBCR(S)Peter Maydell
Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32 TTBCR(S) register if the guest used non-LPAE page tables. This is because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS, meaning that the AArch64 variant has to handle migration and reset. Although AArch64 TCR_EL3 doesn't need to care about the mask and base_mask fields, AArch32 may do so, and so we must use the special TTBCR reset and raw write functions to ensure they are set correctly. This doesn't affect TCR_EL2, because the AArch32 equivalent of that is HTCR, which never uses the non-LPAE page table variant. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Pranith Kumar <bobby.prani+qemu@gmail.com> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1465488181-31977-1-git-send-email-peter.maydell@linaro.org
2016-06-14hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI tableShannon Zhao
Add PMU IRQ number in ACPI table, then we can use PMU in guest through ACPI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465267577-1808-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14hw/arm/virt: Add PMU node for virt machineShannon Zhao
Add a virtual PMU device for virt machine while use PPI 7 for PMU overflow interrupt number. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465267577-1808-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14target-arm: kvm64: set guest PMUv3 feature bit if supportedShannon Zhao
Check if kvm supports guest PMUv3. If so, set the corresponding feature bit for vcpu. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465267577-1808-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14qdev_try_create(): Assert that devices we put onto the system bus are ↵Peter Maydell
SysBusDevices If qdev_try_create() is passed NULL for the bus, it will automatically put the newly created device onto the default system bus. However if the device is not actually a SysBusDevice then this will result in later crashes (for instance when running the monitor "info qtree" command) because code reasonably assumes that all devices on the system bus are system bus devices. Generally the mistake is that the calling code should create the object with object_new(TYPE_FOO) rather than qdev_create(NULL, TYPE_FOO); see commit 6749695eaaf346c1 for an example of fixing this bug. Assert in qdev_try_create() if the device isn't suitable to put on the system bus, so that this mistake results in failure earlier and more reliably. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2016-06-14Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160614' into stagingPeter Maydell
More s390x patches, this time mostly dealing with channel I/O: Bugfixes and cleanups, and dequeue pending interrupts after machine checks. # gpg: Signature made Tue 14 Jun 2016 13:09:43 BST # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20160614: s390x/kvm: Fixup interrupt type for non-adapter I/O interrupts s390x: Limit s390-ccw machines to 248 CPUs virtio-ccw: Provide traces for indicator changes s390x/css: introduce property type for device ids s390x/css: clear IO irqs when generating IPI CRW s390x/kvm: add interface for clearing IO irqs linux-headers: update Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14s390x/kvm: Fixup interrupt type for non-adapter I/O interruptsChristian Borntraeger
The current algorithm for I/O interrupts would result in a wrong interrupt type for subchannel numbers fffe and ffff. In addition a non adapter interrupt might look like an adapter interrupt for any subchannel number that has the 0x0400 bit set. No kernel has ever used the type outside logging - and the logging was wrong all the time. For everything else the kernel used the interrupt parameters. Let's use the KVM_S390_INT_IO macro as for adapter interrupts. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14s390x: Limit s390-ccw machines to 248 CPUsChristian Borntraeger
The sclp scp read info call fills in a buffer with information about the system. With more than 248 CPUs we overflow the 4k buffer of the SCCB, leading to random data corruption. Basically ALL guest operating systems call scp read info, so let's limit the machines to 248 CPUs to make it obvious that >=249 does not work. As KVM also limits itself to 248 and TCG on s390 does not support SMP, this should cause no regression for any user as no VMs with more than 248 VCPUs were ever possible. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by: Boris Fiuczynski <fiuczy@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14virtio-ccw: Provide traces for indicator changesChristian Borntraeger
This allows to trace changes in the summary and queue indicators for the non-irqfd case. For irqfd, kernel traces are needed instead. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14s390x/css: introduce property type for device idsCornelia Huck
Let's introduce a CssDevId to handle device ids of the xx.x.xxxx type used for channel devices. This has some benefits: - We can use them in virtio-ccw and split the validity checks for a channel device id in general from the constraint checking within the virtio-ccw scope. - We can reuse the device id type for future non-virtio channel devices. While we're at it, improve the validity checks and disallow e.g. trailing characters. Suggested-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Acked-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14s390x/css: clear IO irqs when generating IPI CRWHalil Pasic
According to the Principles of Operation (more precisely the subsection 'Channel-Report Word'), a subchannel put into the installed parameters initialized state is in the same state as after an I/O system reset (just parameters possibly changed). This implies that any I/O interrupts for that subchannel are no longer pending (as I/O system resets clear I/O interrupts). Therefore, we need an interface to clear pending I/O interrupts. Make css_generate_sch_crws clear the pending IO interrupts for the subchannel. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14s390x/kvm: add interface for clearing IO irqsHalil Pasic
According to the platform specification, under certain conditions, pending IO interruptions have to be cleared. Let's add an interface for that. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14linux-headers: updateCornelia Huck
Update to 4.7-rc2. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-14Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160614' ↵Peter Maydell
into staging ppc patch queue for 2016-06-14 Latest patch queue for ppc. * Allow qemu to support a generic architecture 2.07 (POWER8-era) compatibility mode. This is useful for guests which are POWER8 aware, but don't know about the specific POWER8 variant that qemu (and/or KVM) is emulating. (Thomas Huth) * Fix a bug where macio wasn't removing DMA mappings (Mark Cave-Ayland) * Add a workaround for Linux guest's miscalculation of maximum memory address (including hotplugged memory), which could break when hotplug memory was combined with VFIO. The previous approach was technically correct by spec, but differed from PowerVM's behaviour enough to trip a guest kernel bug. This works around the bug, while remaining correct-to-spec. (Bharata Rao) # gpg: Signature made Tue 14 Jun 2016 06:53:58 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160614: spapr: Ensure all LMBs are represented in ibm,dynamic-memory macio: call dma_memory_unmap() at the end of each DMA transfer Add PowerPC AT_HWCAP2 definitions ppc: Add PowerISA 2.07 compatibility mode ppc: Improve PCR bit selection in ppc_set_compat() ppc: Provide function to get CPU class of the host CPU ppc: Split pcr_mask settings into supported bits and the register mask ppc/spapr: Refactor h_client_architecture_support() CPU parsing code Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-14spapr: Ensure all LMBs are represented in ibm,dynamic-memoryBharata B Rao
Memory hotplug can fail for some combinations of RAM and maxmem when DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends on maximum addressable memory returned by guest and this value is currently being calculated wrongly by the guest kernel routine memory_hotplug_max(). While there is an attempt to fix the guest kernel, this patch works around the problem within QEMU itself. memory_hotplug_max() routine in the guest kernel arrives at max addressable memory by multiplying lmb-size with the lmb-count obtained from ibm,dynamic-memory property. There are two assumptions here: - All LMBs are part of ibm,dynamic memory: This is not true for PowerKVM where only hot-pluggable LMBs are present in this property. - The memory area comprising of RAM and hotplug region is contiguous: This needn't be true always for PowerKVM as there can be gap between boot time RAM and hotplug region. To work around this guest kernel bug, ensure that ibm,dynamic-memory has information about all the LMBs (RMA, boot-time LMBs, future hotpluggable LMBs, and dummy LMBs to cover the gap between RAM and hotpluggable region). RMA is represented separately by memory@0 node. Hence mark RMA LMBs and also the LMBs for the gap b/n RAM and hotpluggable region as reserved and as having no valid DRC so that these LMBs are not considered by the guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Nathan Fontenot <nfont@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14macio: call dma_memory_unmap() at the end of each DMA transferMark Cave-Ayland
This ensures that the underlying memory is marked dirty once the transfer is complete and resolves cache coherency problems under MacOS 9. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14Add PowerPC AT_HWCAP2 definitionsAnton Blanchard
We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so add the PowerPC AT_HWCAP2 definitions. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth
Make sure that guests can use the PowerISA 2.07 CPU sPAPR compatibility mode when they request it and the target CPU supports it. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Improve PCR bit selection in ppc_set_compat()Thomas Huth
When using an olderr PowerISA level, all the upper compatibility bits have to be enabled, too. For example when we want to run something in PowerISA 2.05 compatibility mode on POWER8, the bit for 2.06 has to be set beside the bit for 2.05. Additionally, to make sure that we do not set bits that are not supported by the host, we apply a mask with the known-to-be-good bits here, too. Signed-off-by: Thomas Huth <thuth@redhat.com> [dwg: Added some #ifs to fix compile on 32-bit targets] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Provide function to get CPU class of the host CPUThomas Huth
When running with KVM, we might be interested in some details of the host CPU class, too, so provide a function to get the corresponding CPU class. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth
The current pcr_mask values are ambiguous: Should these be the mask that defines valid bits in the PCR register? Or should these rather indicate which compatibility levels are possible? Anyway, POWER6 and POWER7 should certainly not use the same values here. So let's introduce an additional variable "pcr_supported" here which is used to indicate the valid compatibility levels, and use pcr_mask to signal the valid bits in the PCR register. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc/spapr: Refactor h_client_architecture_support() CPU parsing codeThomas Huth
The h_client_architecture_support() function has become quite big and nested already. So factor out the code that takes care of the sPAPR compatibility PVRs (which will be modified by the following patches). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-13Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20160613-1' into ↵Peter Maydell
staging usb: misc fixes. # gpg: Signature made Mon 13 Jun 2016 14:09:15 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-usb-20160613-1: vl: Eliminate usb_enabled() pxa2xx: Unconditionally enable USB controller hw/usb/dev-network.c: Use ldl_le_p() and stl_le_p() usb-host: add special case for bus+addr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-13Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/qcrypto-next-2016-06-13-v1' into staging Merge qcrypto-next 2016/06/13 v1 # gpg: Signature made Mon 13 Jun 2016 12:43:22 BST # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qcrypto-next-2016-06-13-v1: crypto: aes: always rename internal symbols crypto: assert that qcrypto_hash_digest_len is in range crypto: remove temp files on completion of secrets test TLS: provide slightly more information when TLS certificate loading fails Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-13crypto: aes: always rename internal symbolsMike Frysinger
OpenSSL's libcrypto always defines AES symbols with the same names as qemu's local aes code. This is problematic when enabling at least curl as that frequently also uses libcrypto. It might not be noticed when running, but if you try to statically link, everything falls down. An example snippet: LINK qemu-nbd .../libcrypto.a(aes-x86_64.o): In function 'AES_encrypt': (.text+0x460): multiple definition of 'AES_encrypt' crypto/aes.o:aes.c:(.text+0x670): first defined here .../libcrypto.a(aes-x86_64.o): In function 'AES_decrypt': (.text+0x9f0): multiple definition of 'AES_decrypt' crypto/aes.o:aes.c:(.text+0xb30): first defined here .../libcrypto.a(aes-x86_64.o): In function 'AES_cbc_encrypt': (.text+0xf90): multiple definition of 'AES_cbc_encrypt' crypto/aes.o:aes.c:(.text+0xff0): first defined here collect2: error: ld returned 1 exit status .../qemu-2.6.0/rules.mak:105: recipe for target 'qemu-nbd' failed make: *** [qemu-nbd] Error 1 The aes.h header has redefines already for FreeBSD, but go ahead and enable that for everyone since there's no real good reason to not use a namespace all the time. Signed-off-by: Mike Frysinger <vapier@chromium.org> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2016-06-13crypto: assert that qcrypto_hash_digest_len is in rangePaolo Bonzini
Otherwise unintended results could happen. For example, Coverity reports a division by zero in qcrypto_afsplit_hash. While this cannot really happen, it shows that the contract of qcrypto_hash_digest_len can be improved. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2016-06-13crypto: remove temp files on completion of secrets testDaniel P. Berrange
The secret object tests left some temporary files on disk when completing. Ensure they are unlink, and rename them to make it more obvious where they come from. Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2016-06-13TLS: provide slightly more information when TLS certificate loading failsAlex Bligh
Give slightly more information when certification loading fails. Rather than have no information, you now get gnutls's only slightly less unhelpful error messages. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2016-06-13vl: Eliminate usb_enabled()Eduardo Habkost
This wrapper for machine_usb(current_machine) is not necessary, replace all usages of usb_enabled() with machine_usb(). Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: qemu-arm@nongnu.org Cc: qemu-ppc@nongnu.org Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 1465419025-21519-3-git-send-email-ehabkost@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-13pxa2xx: Unconditionally enable USB controllerEduardo Habkost
Simplify initialization logic by removing the usb_enabled() check. The USB controller is part of the SoC, so it doesn't make sense to create a system where it is not present. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: qemu-arm@nongnu.org, Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465419025-21519-2-git-send-email-ehabkost@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-13hw/usb/dev-network.c: Use ldl_le_p() and stl_le_p()Peter Maydell
Use stl_le_p() and ldl_le_p() to read and write data from buffers, rather than using pointer casts and cpu_to_le32() for writes and le32_to_cpup() for reads. This: * avoids lots of casts * works even if the buffer isn't as aligned as the host would like * avoids using the *_to_cpup() functions which we want to get rid of Note that there may still be some places where a pointer from the guest is cast to a pointer to a host structure; these would also have to be changed for the device to work on a host CPU which enforces alignment restrictions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1465573077-29221-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-06-13Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160613-tag' ↵Peter Maydell
into staging Xen 2016/06/13 # gpg: Signature made Mon 13 Jun 2016 11:53:18 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20160613-tag: Introduce "xen-load-devices-state" exec: Fix qemu_ram_block_from_host for Xen Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-13usb-host: add special case for bus+addrGerd Hoffmann
This patch changes usb-host behavior in case we hostbus= and hostaddr= properties are used to identify the usb device in question. Instead of adding the device to the hotplug watchlist we try to open directly using the given bus number and device address. Putting a device specified by hostaddr to the hotplug watchlist isn't a great idea as the address isn't a fixed property. It changes every time the device is plugged in. So considering this case as "use the device at bus:addr _now_" is more sane. Also usb-host will throw errors in case it can't initialize the host device. Note: For devices on the hotplug watchlist (hostport or vendorid or productid specified) qemu continues to ignore errors and keeps monitoring the usb bus to see if the device eventually shows up. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1464945175-28939-1-git-send-email-kraxel@redhat.com
2016-06-13Introduce "xen-load-devices-state"Wen Congyang
Introduce a "xen-load-devices-state" QAPI command that can be used to load the state of all devices, but not the RAM or the block devices of the VM. We only have hmp commands savevm/loadvm, and qmp commands xen-save-devices-state. We use this new command for COLO: 1. suspend both primary vm and secondary vm 2. sync the state 3. resume both primary vm and secondary vm In such case, we need to update all devices' state in any time. Signed-off-by: Wen Congyang <wency@cn.fujitsu.com> Signed-off-by: Changlong Xie <xiecl.fnst@cn.fujitsu.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2016-06-13exec: Fix qemu_ram_block_from_host for XenAnthony PERARD
Since f615f39 (exec: remove ram_addr argument from qemu_ram_block_from_host), migration under Xen is likely to fail, with a SEGV of QEMU. But the commit only reveal a bug with the calculation of the offset value in qemu_ram_block_from_host(). This patch calculates the offset from the ram_addr as qemu_ram_addr_from_host() will later calculate the ram_addr from the offset. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2016-06-13Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160611' into stagingPeter Maydell
TB hashing improvements # gpg: Signature made Sun 12 Jun 2016 01:12:50 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20160611: translate-all: add tb hash bucket info to 'info jit' dump tb hash: track translated blocks with qht qht: add test-qht-par to invoke qht-bench from 'check' target qht: add qht-bench, a performance benchmark qht: add test program qht: QEMU's fast, resizable and scalable Hash Table qdist: add test program qdist: add module to represent frequency distributions of data tb hash: hash phys_pc, pc, and flags with xxhash exec: add tb_hash_func5, derived from xxhash qemu-thread: add simple test-and-set spinlock include/processor.h: define cpu_relax() seqlock: rename write_lock/unlock to write_begin/end seqlock: remove optional mutex compiler.h: add QEMU_ALIGNED() to enforce struct alignment Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-11translate-all: add tb hash bucket info to 'info jit' dumpEmilio G. Cota
Examples: - Good hashing, i.e. tb_hash_func5(phys_pc, pc, flags): TB count 715135/2684354 [...] TB hash buckets 388775/524288 (74.15% head buckets used) TB hash occupancy 33.04% avg chain occ. Histogram: [0,10)%|▆ █ ▅▁▃▁▁|[90,100]% TB hash avg chain 1.017 buckets. Histogram: 1|█▁▁|3 - Not-so-good hashing, i.e. tb_hash_func5(phys_pc, pc, 0): TB count 712636/2684354 [...] TB hash buckets 344924/524288 (65.79% head buckets used) TB hash occupancy 31.64% avg chain occ. Histogram: [0,10)%|█ ▆ ▅▁▃▁▂|[90,100]% TB hash avg chain 1.047 buckets. Histogram: 1|█▁▁▁|4 - Bad hashing, i.e. tb_hash_func5(phys_pc, 0, 0): TB count 702818/2684354 [...] TB hash buckets 112741/524288 (21.50% head buckets used) TB hash occupancy 10.15% avg chain occ. Histogram: [0,10)%|█ ▁ ▁▁▁▁▁|[90,100]% TB hash avg chain 2.107 buckets. Histogram: [1.0,10.2)|█▁▁▁▁▁▁▁▁▁|[83.8,93.0] - Good hashing, but no auto-resize: TB count 715634/2684354 TB hash buckets 8192/8192 (100.00% head buckets used) TB hash occupancy 98.30% avg chain occ. Histogram: [95.3,95.8)%|▁▁▃▄▃▄▁▇▁█|[99.5,100.0]% TB hash avg chain 22.070 buckets. Histogram: [15.0,16.7)|▁▂▅▄█▅▁▁▁▁|[30.3,32.0] Acked-by: Sergey Fedorov <sergey.fedorov@linaro.org> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1465412133-3029-16-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-06-11tb hash: track translated blocks with qhtEmilio G. Cota
Having a fixed-size hash table for keeping track of all translation blocks is suboptimal: some workloads are just too big or too small to get maximum performance from the hash table. The MRU promotion policy helps improve performance when the hash table is a little undersized, but it cannot make up for severely undersized hash tables. Furthermore, frequent MRU promotions result in writes that are a scalability bottleneck. For scalability, lookups should only perform reads, not writes. This is not a big deal for now, but it will become one once MTTCG matures. The appended fixes these issues by using qht as the implementation of the TB hash table. This solution is superior to other alternatives considered, namely: - master: implementation in QEMU before this patchset - xxhash: before this patch, i.e. fixed buckets + xxhash hashing + MRU. - xxhash-rcu: fixed buckets + xxhash + RCU list + MRU. MRU is implemented here by adding an intermediate struct that contains the u32 hash and a pointer to the TB; this allows us, on an MRU promotion, to copy said struct (that is not at the head), and put this new copy at the head. After a grace period, the original non-head struct can be eliminated, and after another grace period, freed. - qht-fixed-nomru: fixed buckets + xxhash + qht without auto-resize + no MRU for lookups; MRU for inserts. The appended solution is the following: - qht-dyn-nomru: dynamic number of buckets + xxhash + qht w/ auto-resize + no MRU for lookups; MRU for inserts. The plots below compare the considered solutions. The Y axis shows the boot time (in seconds) of a debian jessie image with arm-softmmu; the X axis sweeps the number of buckets (or initial number of buckets for qht-autoresize). The plots in PNG format (and with errorbars) can be seen here: http://imgur.com/a/Awgnq Each test runs 5 times, and the entire QEMU process is pinned to a single core for repeatability of results. Host: Intel Xeon E5-2690 28 ++------------+-------------+-------------+-------------+------------++ A***** + + + master **A*** + 27 ++ * xxhash ##B###++ | A******A****** xxhash-rcu $$C$$$ | 26 C$$ A******A****** qht-fixed-nomru*%%D%%%++ D%%$$ A******A******A*qht-dyn-mru A*E****A 25 ++ %%$$ qht-dyn-nomru &&F&&&++ B#####% | 24 ++ #C$$$$$ ++ | B### $ | | ## C$$$$$$ | 23 ++ # C$$$$$$ ++ | B###### C$$$$$$ %%%D 22 ++ %B###### C$$$$$$C$$$$$$C$$$$$$C$$$$$$C$$$$$$C | D%%%%%%B###### @E@@@@@@ %%%D%%%@@@E@@@@@@E 21 E@@@@@@E@@@@@@F&&&@@@E@@@&&&D%%%%%%B######B######B######B######B######B + E@@@ F&&& + E@ + F&&& + + 20 ++------------+-------------+-------------+-------------+------------++ 14 16 18 20 22 24 log2 number of buckets Host: Intel i7-4790K 14.5 ++------------+------------+-------------+------------+------------++ A** + + + master **A*** + 14 ++ ** xxhash ##B###++ 13.5 ++ ** xxhash-rcu $$C$$$++ | qht-fixed-nomru %%D%%% | 13 ++ A****** qht-dyn-mru @@E@@@++ | A*****A******A****** qht-dyn-nomru &&F&&& | 12.5 C$$ A******A******A*****A****** ***A 12 ++ $$ A*** ++ D%%% $$ | 11.5 ++ %% ++ B### %C$$$$$$ | 11 ++ ## D%%%%% C$$$$$ ++ | # % C$$$$$$ | 10.5 F&&&&&&B######D%%%%% C$$$$$$C$$$$$$C$$$$$$C$$$$$C$$$$$$ $$$C 10 E@@@@@@E@@@@@@B#####B######B######E@@@@@@E@@@%%%D%%%%%D%%%###B######B + F&& D%%%%%%B######B######B#####B###@@@D%%% + 9.5 ++------------+------------+-------------+------------+------------++ 14 16 18 20 22 24 log2 number of buckets Note that the original point before this patch series is X=15 for "master"; the little sensitivity to the increased number of buckets is due to the poor hashing function in master. xxhash-rcu has significant overhead due to the constant churn of allocating and deallocating intermediate structs for implementing MRU. An alternative would be do consider failed lookups as "maybe not there", and then acquire the external lock (tb_lock in this case) to really confirm that there was indeed a failed lookup. This, however, would not be enough to implement dynamic resizing--this is more complex: see "Resizable, Scalable, Concurrent Hash Tables via Relativistic Programming" by Triplett, McKenney and Walpole. This solution was discarded due to the very coarse RCU read critical sections that we have in MTTCG; resizing requires waiting for readers after every pointer update, and resizes require many pointer updates, so this would quickly become prohibitive. qht-fixed-nomru shows that MRU promotion is advisable for undersized hash tables. However, qht-dyn-mru shows that MRU promotion is not important if the hash table is properly sized: there is virtually no difference in performance between qht-dyn-nomru and qht-dyn-mru. Before this patch, we're at X=15 on "xxhash"; after this patch, we're at X=15 @ qht-dyn-nomru. This patch thus matches the best performance that we can achieve with optimum sizing of the hash table, while keeping the hash table scalable for readers. The improvement we get before and after this patch for booting debian jessie with arm-softmmu is: - Intel Xeon E5-2690: 10.5% less time - Intel i7-4790K: 5.2% less time We could get this same improvement _for this particular workload_ by statically increasing the size of the hash table. But this would hurt workloads that do not need a large hash table. The dynamic (upward) resizing allows us to start small and enlarge the hash table as needed. A quick note on downsizing: the table is resized back to 2**15 buckets on every tb_flush; this makes sense because it is not guaranteed that the table will reach the same number of TBs later on (e.g. most bootup code is thrown away after boot); it makes sense to grow the hash table as more code blocks are translated. This also avoids the complication of having to build downsizing hysteresis logic into qht. Reviewed-by: Sergey Fedorov <serge.fedorov@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1465412133-3029-15-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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