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2012-04-15target-ppc/machine.c: Drop unnecessary ifdefsJuan Quintela
machine.c is only compiled for softmmu targets, so checks for !defined(CONFIG_USER_ONLY) are unnecessary and can be dropped. Signed-off-by: Juan Quintela <quintela@redhat.com> [AF: Use more verbose commit message suggested by PMM] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Init dcache and icache size for e500 user modeMeador Inge
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icache line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block. This is not correct because instructions like 'dcbz' need the dcache size initialized even for user mode. Signed-off-by: Meador Inge <meadori@codesourcery.com> Cc: Varun Sethi <Varun.Sethi@freescale.com> [AF: Simplify #ifdefs by using cache line size 32 for *-user as before] Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil
This changes nothing for other hosts. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: QOM'ify CPU resetAndreas Färber
Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Start QOM'ifying CPU initAndreas Färber
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: QOM'ify CPUAndreas Färber
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson
On target-ppc, our table of CPU types and features encodes the features as found on the hardware, regardless of whether these features are actually usable under TCG or KVM. We already have cases where the information from the cpu table must be fixed up to account for limitations in the emulation method we're using. e.g. TCG does not support the DFP and VSX instructions and KVM needs different numbering of the CPUs in order to tell it the correct thread to core mappings. This patch cleans up these hacks to handle emulation limitations by consolidating them into a pair of functions specifically for the purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [AF: Style and typo fixes, rename new functions and drop ppc_def_t arg] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15target-ppc: Drop cpu_ppc_close()Andreas Färber
It is unused, so avoid QOM'ifying it unneededly. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
2012-04-15pseries: Consolidate hack for RTAS display-character usageDavid Gibson
Currently the pseries machine contains not one but two somewhat ugly hacks to allow printing of early debug messages before the guest has properly read the device tree. First, we special case H_PUT_TERM_CHAR so that a vtermno of 0 (usually invalid) will look for a suitable vty and use that. This supports Linux's early debug code which will use H_PUT_TERM_CHAR with vtermno==0 before reading the device tree. Second, we support the RTAS display-character call. This takes no vtermno so we assume the address of the default first VTY. This patch makes things more consistent by folding the second hack into the first. Now, display-character uses the existing vty_lookup() function to do the same search for a suitable VTY. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15pseries: Remove unused fields from VIOsPAPRBus structureDavid Gibson
The VIOsPAPRBus structure, used on the pseries machine contains some old fields which are no longer used anywhere. This patch removes them. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15pseries: Implement RTAS system-reboot callDavid Gibson
This patch adds the PAPR defined RTAS system-reboot call to the pseries machine emulation, providing the guest with a way to trigger a reboot. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15pseries: Fix bug with reset of VIO CRQsDavid Gibson
PAPR specifies a Command Response Queue (CRQ) mechanism used for virtual IO, which we implement. However, we don't correctly clean up registered CRQs when we reset the system. This patch adds a reset handler to fix this bug. While we're at it, add in some of the extra debug messages that were used to track the problem down. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [AF: Updated hcall_dprintf()s to not duplicate the function name] Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15pseries: Clean up hcall_dprintf() debugging messagesDavid Gibson
The pseries machine code has a number of debug messages for debugging PAPR hypercalls, dependent on DEBUG_SPAPR_HCALLS. This patch cleans these messages up a bit, by adding __func__ to the hcall_dprintf() macro and simplifying up a number of the individual messages accordingly. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15PPC: Fix TLB invalidation bug within the PPC interrupt handler.Mark Cave-Ayland
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-15pcspk: initialize PC speaker if compiled inHervé Poussineau
PC speaker has been moved to target-independant code in 71093711589dafcb920dc3bc9bb811eaf8b14101, so do not depend of target to include it or not. Cc: malc <av1474@comtv.ru> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Herv? Poussineau <hpoussin@reactos.org> Signed-off-by: malc <av1474@comtv.ru>
2012-04-14tests: remove .SECONDARY special targetPaolo Bonzini
The special target should not be needed anymore, and caused (perhaps due to a Make bug) a failure with "make -j2". In any case, the main makefile is a better place for such special targets rather than an included makefile. Reported-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14target-xtensa: add test for IBREAK invalidationMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14target-xtensa: add tests for LBEG/LEND invalidationMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov
Instruction breakpoint/zero overhead loop handling code is built into TBs pointed to by IBREAKA/LEND SRs. When these or related SRs get changed TBs at virtual addresses corresponding to their old and their new values must be invalidated. Virtual address range is passed to the tb_invalidate_phys_page_range, which is incorrect in system emulation mode. To fix it use guest TLB/MMU to translate virtual address to physical address. However the guest may not have virtual-to-physical mapping at the moment of IBREAKA/LEND change, thus this fix is not 100% accurate. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14exec: provide tb_invalidate_phys_addr functionMax Filippov
Allow TB invalidation by its physical address, extract implementation from the breakpoint_invalidate function. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14Use uintptr_t for various op related functionsBlue Swirl
Use uintptr_t instead of void * or unsigned long in several op related functions, env->mem_io_pc and GETPC() macro. Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14coroutine-gthread.c: Avoid threading APIs deprecated in GLib 2.31Peter Maydell
The GLib threading APIs were revamped in GLib 2.31 and a number of the old interfaces were deprecated, which means they provoke compilation warnings (errors if -Werror) now. Add support for the new interfaces while retaining the old ones so we can still compile on older versions of GLib too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensaBlue Swirl
* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa: target-xtensa: Start QOM'ifying CPU init target-xtensa: QOM'ify CPU reset target-xtensa: QOM'ify CPU target-xtensa: improve unit tests debugging target-xtensa: Move helpers.h to helper.h
2012-04-14Merge branch 'arm-devs.for-upstream' of ↵Blue Swirl
git://git.linaro.org/people/pmaydell/qemu-arm * 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: hw/arm_gic: Remove stray hardcoded tab hw/arm_gic: gic_set_pending_private() is NVIC only hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC define hw/arm_gic: Make gic_reset a sysbus reset function hw/arm11mpcore: Convert to using sysbus GIC device hw/exynos4210_gic: Convert to using sysbus GIC hw/realview_gic: switch to sysbus GIC hw/a9mpcore: Switch to using sysbus GIC hw/a15mpcore: switch to using sysbus GIC hw/arm_gic: Make the GIC its own sysbus device hw/arm_gic: Expose PPI inputs as gpio inputs hw/arm_gic: Move gic_get_current_cpu into arm_gic.c hw/arm_gic: Move NCPU definition to arm_gic.c hw/exynos4210_combiner.c: Drop excessive read/write access check. ARM: Exynos4210: Drop gic_cpu_write() after initialization. Fix bit test in Exynos4210 UART emulation to use & instead of &&
2012-04-14target-xtensa: Start QOM'ifying CPU initAndreas Färber
Move XtensaConfig-independent code from cpu_xtensa_init() into a QOM initfn, as a start. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber
Move code from cpu_state_reset() into QOM xtensa_cpu_reset(). To avoid moving reset_mmu() and dependencies, make it non-static. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber
Embed CPUXtensaState as first member of XtensaCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: improve unit tests debuggingMax Filippov
- add testcase announcement; - add global symbols for individual tests; - add host-debug-* makefile target. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova
Provides a file naming scheme consistent with other targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-13Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori
* stefanha/trivial-patches: configure: Insist on a Python 2, not Python 3 bsd-user: fix compile failure ps2: avoid repeated header file includes make: Always set LC_ALL=C for makeinfo configure: Fix wrong preprocessor statement configure: Remove useless uses of ARCH_CFLAGS
2012-04-13Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori
* qemu-kvm/uq/master: kvmclock: guest stop notification kvm: update linux headers kvm: set gsi_bits and max_gsi correctly kvm: Drop unused kvm_pit_in_kernel kvm: allow arbitrarily sized mmio ioeventfd kvm: Drop redundant kvm_enabled from cpu_thread_is_idle kvm: add flightrecorder script
2012-04-13Merge remote-tracking branch 'afaerber/qom-cpu-lm32.v3' into stagingAnthony Liguori
* afaerber/qom-cpu-lm32.v3: target-lm32: QOM'ify CPU reset target-lm32: QOM'ify CPU init target-lm32: QOM'ify CPU
2012-04-13hw/arm_gic: Remove stray hardcoded tabPeter Maydell
Remove the single instance of a hardcoded tab from hw/arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: gic_set_pending_private() is NVIC onlyPeter Maydell
The function gic_set_pending_private() is now used by the NVIC only (for the GIC we now set PPI interrupts via gpio lines and gic_set_irq()). So make it #ifdef NVIC and remove the 'attribute unused' annotation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC definePeter Maydell
Now all the A profile cores have been switched to use the standalone sysbus GIC, the only remaining code which #includes arm_gic.c is the v7M NVIC. The coupling is much closer here so it's not so easily disentangled. For now, add a comment about how arm_gic.c is compiled, and assume that the NVIC always includes arm_gic.c and the non-NVIC GIC is always compiled standalone. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make gic_reset a sysbus reset functionPeter Maydell
Make gic_reset a sysbus reset function, so we actually reset the GIC on system reset rather than only at init. For the NVIC this requires us also to implement reset of the SysTick. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm11mpcore: Convert to using sysbus GIC devicePeter Maydell
Convert arm11mpcore to using the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/exynos4210_gic: Convert to using sysbus GICPeter Maydell
Convert the Exynos GIC code to use the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/realview_gic: switch to sysbus GICPeter Maydell
Switch the realview_gic device to the standalone sysbus GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/a9mpcore: Switch to using sysbus GICPeter Maydell
Switch the a9mpcore to using the sysbus GIC device rather than having the a9mp private memory region device subclass the GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/a15mpcore: switch to using sysbus GICPeter Maydell
Switch the a15mpcore private peripheral region to using the standalone sysbus GIC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make the GIC its own sysbus devicePeter Maydell
Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Expose PPI inputs as gpio inputsPeter Maydell
Expose the Private Peripheral Interrupt inputs as GPIO inputs. The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ... Treating PPIs as being another kind of input line is in line with the GIC architecture specification, where they are clearly described that way. The 11MPCore TRM is a bit more ambiguous, but there is no practical difference between "set PPI X as pending" and "0->1 transition on a PPI input line configured as edge triggered", and PPIs are always edge triggered, so this change won't affect behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Move gic_get_current_cpu into arm_gic.cPeter Maydell
Move the gic_get_current_cpu() function into arm_gic.c. There are only two implementations: (1) "get the index of the currently executing CPU", used by all multicore GICs, and (2) "always 0", used by all GICs instantiated with a single CPU interface (the Realview board GIC and the v7M NVIC). So we can move this into the main GIC source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Move NCPU definition to arm_gic.cPeter Maydell
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/exynos4210_combiner.c: Drop excessive read/write access check.Evgeny Voevodin
Access to reserved area at offset higher than 0x3c is allowed in External Combiner. Samsung Galaxy Kernel implements this. So, drop excessive checks in read/write functions. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13ARM: Exynos4210: Drop gic_cpu_write() after initialization.Evgeny Voevodin
Remove gic_cpu_write() call after initialization that was emulating functionality of earliest SOC bootloader which enables external GIC CPU1 interface. Instead introduce Exynos4210-specific secondary CPU bootloader, which enables both Internal and External GIC CPU1 interfaces. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13Fix bit test in Exynos4210 UART emulation to use & instead of &&Daniel P. Berrange
* hw/exynos4210_uart.c: s/&&/&/ Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13configure: Insist on a Python 2, not Python 3Peter Maydell
Our Python scripts require Python 2 and will fail on Python 3, eg: File "/home/petmay01/linaro/qemu-from-laptop/qemu/scripts/qapi-commands.py", line 378 except getopt.GetoptError, err: ^ SyntaxError: invalid syntax Add a check to configure that Python is not a Python 3, so we can fail with a comprehensible error rather than an obscure one. Reported-by: Boris Matti <swiftos@lavabit.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-04-13bsd-user: fix compile failurePeter Maydell
bsd-user doesn't actually support reserving a memory area for the guest address space, but we need to at least define the reserved_va global so that cpu-all.h's RESERVED_VA macro will work correctly. This fixes a compilation error introduced in commit 39879bb which added a use of RESERVED_VA to h2g_valid(). Reported-by: Brad Smith <brad@comstyle.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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