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2014-12-12block: vhdx - change .vhdx_create default block state to ZEROJeff Cody
The VHDX spec specifies that the default new block state is PAYLOAD_BLOCK_NOT_PRESENT for a dynamic VHDX image, and PAYLOAD_BLOCK_FULLY_PRESENT for a fixed VHDX image. However, in order to create space-efficient VHDX images with qemu-img convert, it is desirable to be able to set has_zero_init to true for VHDX. There is currently an option when creating VHDX images, to use block state ZERO for new blocks. However, this currently defaults to 'off'. In order to be able to eventually set has_zero_init to true for VHDX, this needs to default to 'on'. This patch changes the default to 'on', and provides some help information to warn against setting it to 'off' when using qemu-img convert. [Max Reitz pointed out that a full stop was missing at the end of the VHDX_BLOCK_OPT_ZERO option help text. I have added it. --Stefan] Signed-off-by: Jeff Cody <jcody@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 85164899eacc86e150c3ceba793cf93b398dedd7.1418018421.git.jcody@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12block: vhdx - update PAYLOAD_BLOCK_UNMAPPED value to match 1.00 specJeff Cody
The 0.95 VHDX spec defined PAYLOAD_BLOCK_UNMAPPED to be 5. The 1.00 VHDX spec redefines PAYLOAD_BLOCK_UNMAPPED to be 3 instead. The original value of 5 is now an undefined state in the spec, but it should be safe to treat it the same and return zeros for data read. This way, we can maintain compatibility with any images out in the wild that may have been created in accordance to the 0.95 spec. Reported-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Jeff Cody <jcody@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 8a4d2da73a8dbc04cde62bea782fc09ff84b1cf1.1418018421.git.jcody@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12block: vhdx - remove redundant commentsJeff Cody
Minor cleanup. Signed-off-by: Jeff Cody <jcody@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: e8718ae3fd3e40a527e46a00e394973fbaab4d53.1418018421.git.jcody@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12block/rbd: fix memory leakGonglei
Variable local_err going out of scope leaks the storage it points to. Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Amos Kong <akong@redhat.com> Message-id: 1417674851-6248-1-git-send-email-arei.gonglei@huawei.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12iotests: Add test for vmdk JSON file namesMax Reitz
Add a test for vmdk files which use a file with a JSON file name, and which then try to open extents. That should fail and the error message should at least try to look helpful. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1417615043-26174-3-git-send-email-mreitz@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12vmdk: Fix error for JSON descriptor file namesMax Reitz
If vmdk blindly tries to use path_combine() using bs->file->filename as the base file name, this will result in a bad error message for JSON file names when calling bdrv_open(). It is better to only try bs->file->exact_filename; if that is empty, bs->file->filename will be useless for path_combine() and an error should be emitted (containing bs->file->filename because desc_file_path (which is bs->file->exact_filename) is empty). Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Message-id: 1417615043-26174-2-git-send-email-mreitz@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-12block migration: fix return valueGary R Hook
Modify block_save_iterate() to return positive/zero/negative (success/not done/failure) return status. The computation of the blocks transferred (an int64_t) exceeds the size of an int return value. Signed-off-by: Gary R Hook <gary.hook@nimboxx.com> Reviewed-by: ChenLiang <chenliang88@huawei.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1416958202-15913-1-git-send-email-gary.hook@nimboxx.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-11Merge remote-tracking branch ↵Peter Maydell
'remotes/mjt/tags/pull-trivial-patches-2014-12-11' into staging trivial patches for 2014-12-11 # gpg: Signature made Thu 11 Dec 2014 18:13:58 GMT using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2014-12-11: Sort include/qemu/typedefs.h hpet: increase spelling precision pflash_cfi02.c: associate "cfi.pflash02" to "Storage devices" category vt82c686: fix coverity warning about out-of-bounds write virtio: remove useless declaration of virtio_net_init() qapi-schema: fix typo about change-vnc-password fw_cfg: remove superfluous blank line get_maintainer.pl: Remove the --git-chief-penguins option configure: Replace which(1) with "has" util: Use g_new() & friends where that makes obvious sense util: Fuse g_malloc(); memset() into g_new0() util: Drop superfluous conditionals around g_free() Drop superfluous conditionals around g_strdup() Drop superfluous conditionals around qemu_opts_del() usb: delete redundant brackets in usb_host_handle_control() virtio-bus: avoid breaking build when open DEBUG switch acpi-build: Make DPRINTF working for acpi-build acpi-build: adjust indention 8 -> 4 spaces target-s390x: fix possible out of bounds read qmp: fix typo in input-send-event examples Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Sort include/qemu/typedefs.hDr. David Alan Gilbert
Mainly to make it less likely to conflict during merges. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-12-11hpet: increase spelling precisionStefan Hajnoczi
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-12-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20141211' into staging target-arm queue: * pass semihosting exit code out to system * more TrustZone support code (still not enabled yet) * allow user to direct semihosting to gdb or native explicitly rather than always auto-guessing the destination * fix memory leak in realview_init * fix coverity warning in hw/arm/boot * get state migration working for AArch64 CPUs * check errors in kvm_arm_reset_vcpu # gpg: Signature made Thu 11 Dec 2014 12:16:19 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20141211: (33 commits) target-arm: Check error conditions on kvm_arm_reset_vcpu target-arm: Support save/load for 64 bit CPUs target-arm/kvm: make reg sync code common between kvm32/64 arm_gic_kvm: Tell kernel about number of IRQs hw/arm/boot: fix uninitialized scalar variable warning reported by coverity hw/arm/realview.c: Fix memory leak in realview_init() target-arm: make MAIR0/1 banked target-arm: make c13 cp regs banked (FCSEIDR, ...) target-arm: make VBAR banked target-arm: make PAR banked target-arm: make IFAR/DFAR banked target-arm: make DFSR banked target-arm: make IFSR banked target-arm: make DACR banked target-arm: make TTBCR banked target-arm: make TTBR0/1 banked target-arm: make CSSELR banked target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: add MVBAR support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block patches for 2.3 # gpg: Signature made Wed 10 Dec 2014 09:31:53 GMT using RSA key ID C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" * remotes/kevin/tags/for-upstream: (73 commits) vmdk: Set errp on failures in vmdk_open_vmdk4 vmdk: Remove unnecessary initialization vmdk: Check descriptor file length when reading it vmdk: Clean up descriptor file reading vmdk: Fix comment to match code of extent lines vmdk: Use g_random_int to generate CID block: Use g_new0() for a bit of extra type checking block: remove BLOCK_OPT_NOCOW from vpc_create_opts block: remove BLOCK_OPT_NOCOW from vdi_create_opts qemu-iotests: Skip 099 for VMDK subformats with desc file block/raw-posix: Fix ret in raw_open_common() qcow2: Respect bdrv_truncate() error qcow2: Flushing the caches in qcow2_close may fail qcow2: Prevent numerical overflow iotests: Add test for unsupported image creation iotests: Only kill NBD server if it runs qemu-img: Check create_opts before image amendment qemu-img: Check create_opts before image creation block: Check create_opts before image creation block/nfs: Add create_opts ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: Check error conditions on kvm_arm_reset_vcpuChristoffer Dall
When resetting a VCPU we currently call both kvm_arm_vcpu_init() and write_kvmstate_to_list(), both of which can fail, but we never check the return value. The only choice here is to print an error an exit if the calls fail. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418039630-11773-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: Support save/load for 64 bit CPUsPeter Maydell
For migration to work on 64 bit CPUs, we need to include both the 64-bit integer register file and the PSTATE. Everything else is either stored in the same place as existing 32-bit CPU state or handled by the generic sysreg mechanism. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1417788683-4038-3-git-send-email-peter.maydell@linaro.org
2014-12-11target-arm/kvm: make reg sync code common between kvm32/64Alex Bennée
Before we launch a guest we query KVM for the list of "co-processor" registers it knows about. This is used to synchronize system register state for the bulk of coprocessor/system registers. Move this code from the 32-bit specific vcpu init function into a common routine and call it also from the 64-bit vcpu init. This allows system registers to migrate correctly when using KVM, and also permits QEMU code to see the current KVM register state (which will be needed to support big-endian guests, since the virtio endianness callback must check for some system register settings). Since vcpu reset also has to sync registers, we move the 32 bit kvm_arm_reset_vcpu() into common code as well and share it with the 64 bit version. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [PMM: just copy the 32-bit code rather than improving it along the way; don't share reg_syncs_via_tuple_list() between 32 and 64 bit; tweak function names; move reset] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11arm_gic_kvm: Tell kernel about number of IRQsPeter Maydell
Newer kernels support a device attribute on the GIC which allows us to tell it how many IRQs this GIC instance is configured with; use it, if it exists. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1417718679-1071-1-git-send-email-peter.maydell@linaro.org
2014-12-11hw/arm/boot: fix uninitialized scalar variable warning reported by coverityzhanghailiang
Coverity reports the 'size' may be used uninitialized, but that can't happen, because the caller has checked "if (binfo->dtb_filename || binfo->get_dtb)" before call 'load_dtb'. Here we simply remove the 'if (binfo->get_dtb)' to satisfy coverity. Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Message-id: 1416826240-12368-1-git-send-email-zhang.zhanghailiang@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11hw/arm/realview.c: Fix memory leak in realview_init()Nikita Belov
Variable 'ram_lo' is allocated unconditionally, but used only in some cases. When it is unused pointer will be lost at function exit, resulting in a memory leak. Allocate memory for 'ram_lo' only if it is needed. Valgrind output: ==16879== 240 bytes in 1 blocks are definitely lost in loss record 6,033 of 7,018 ==16879== at 0x4C2AB80: malloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) ==16879== by 0x33D2CE: malloc_and_trace (vl.c:2804) ==16879== by 0x509E610: g_malloc (in /lib/x86_64-linux-gnu/libglib-2.0.so.0.4000.0) ==16879== by 0x288836: realview_init (realview.c:55) ==16879== by 0x28988C: realview_pb_a8_init (realview.c:375) ==16879== by 0x341426: main (vl.c:4413) Signed-off-by: Nikita Belov <zodiac@ispras.ru> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows
Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-26-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-25-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make VBAR bankedGreg Bellows
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-24-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make PAR bankedFabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-23-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFAR and DFAR have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-22-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make DFSR bankedFabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DFSR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-21-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make IFSR bankedFabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-20-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make DACR bankedFabian Aggeler
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) DACR has a secure and a non-secure instance. Adds definition for DACR32_EL2. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-19-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make TTBCR bankedFabian Aggeler
Adds secure and non-secure bank register suport for TTBCR. Added new struct to compartmentalize the TCR data and masks. Removed old tcr/ttbcr data and added a 4 element array of the new structs in cp15. This allows for one entry per EL. Added a CP register definition for TCR_EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-18-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler
Adds secure and non-secure bank register suport for TTBR0 and TTBR1. Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as well as a CP register definition for TTBR0_EL3. Added a union containing both EL based array fields and secure and non-secure fields mapped to them. Updated accesses to use A32_BANKED_CURRENT_REG_GET macro. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-17-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: make CSSELR bankedFabian Aggeler
Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-16-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits are used to control whether the CPSR masking bits can be adjusted from non-secure state. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-15-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when needed. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-14-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add MVBAR supportFabian Aggeler
Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-13-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add SDER definitionGreg Bellows
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-12-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add NSACR registerFabian Aggeler
Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-11-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-10-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension feature. Register that list only for ARM cores with Security Extension/EL3 support. Moving AArch32 SCR into Security Extension register group. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-9-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler
Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-8-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
Added additional NS-bit to CPREG hash encoding. Updated hash lookup locations to specify hash bit currently set to non-secure. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-7-git-send-email-greg.bellows@linaro.org [PMM: fix uses of ENCODE_CP_REG in kvm32.c to add extra argument] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov
This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter <johannes.winter@iaik.tugraz.at>. The TBFLAG captures the SCR NS secure state at the time when a TB is created so the correct bank is accessed on system register accesses. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add banked register accessorsFabian Aggeler
If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: add async excp target_el functionGreg Bellows
Adds a dedicated function and a lookup table for determining the target exception level of IRQ and FIQ exceptions. The lookup table is taken from the ARMv7 and ARMv8 specification exception routing tables. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11target-arm: extend async excp maskingGreg Bellows
This patch extends arm_excp_unmasked() to use lookup tables for determining whether IRQ and FIQ exceptions are masked. The lookup tables are based on the ARMv8 and ARMv7 specification physical interrupt masking tables. If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels other than EL3 if SCR.{FIQ|IRQ} is set to 1 (routed to EL3). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Add the "-semihosting-config" option.Liviu Ionescu
The usual semihosting behaviour is to process the system calls locally and return; unfortuantelly the initial implementation dinamically changed the target to GDB during debug sessions, which, for the usual arm-none-eabi-gdb, is not implemented. The result was that during debug sessions the semihosting calls were discarded. This patch adds a configuration variable and an option to set it on the command line: -semihosting-config [enable=on|off,]target=native|gdb|auto This option enables semihosting and defines where the semihosting calls will be addressed, to QEMU ('native') or to GDB ('gdb'). The default is auto, which means 'gdb' during debug sessions and 'native' otherwise. Signed-off-by: Liviu Ionescu <ilg@livius.net> Message-id: 1416341957-9796-1-git-send-email-ilg@livius.net [PMM: moved declaration and definition of semihosting_target to gdbstub.h and gdbstub.c to fix build failure on linux-user] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Pass semihosting exit code back to system.Liviu Ionescu
In order to run unit tests under semihosting, it is necessary to pass the application exit code back to the system. ARM defines only the code to be used for non-error application exit (ADP_Stopped_ApplicationExit), all other codes should return non-zero exit codes. This patch checks if the application code passed via TARGET_SYS_EXIT is ADP_Stopped_ApplicationExit, and return 0, otherwise return 1. Signed-off-by: Liviu Ionescu <ilg@livius.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Merge remote-tracking branch ↵Peter Maydell
'remotes/bkoppelmann/tags/pull-tricore-20141210' into staging TriCore BOL, BRC, BRN, BRR, RC, RCPW, RCRR, RCR, RLC and RCR insn added # gpg: Signature made Wed 10 Dec 2014 11:21:58 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20141210: target-tricore: Add instructions of RCR opcode format target-tricore: Add instructions of RLC opcode format target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format target-tricore: Make TRICORE_FEATURES implying others. target-tricore: Add instructions of RC opcode format target-tricore: Add instructions of BRR opcode format target-tricore: Add instructions of BRN opcode format target-tricore: Add instructions of BRC opcode format target-tricore: Add instructions of BOL opcode format Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-20141210-1' into ↵Peter Maydell
staging vnc-enc-tight fix, keymaps code style. # gpg: Signature made Wed 10 Dec 2014 09:24:33 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vnc-20141210-1: keymaps: correct keymaps.c following Qemu coding style vnc-enc-tight: fix Arguments in wrong order Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-10pflash_cfi02.c: associate "cfi.pflash02" to "Storage devices" categoryAntony Pavlov
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-12-10target-tricore: Add instructions of RCR opcode formatBastian Koppelmann
Add instructions of RCR opcode format. Add helper for madd32/64_ssov and madd32/64_suov. Add helper for msub32/64_ssov and msub32/64_suov. Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub. OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-10target-tricore: Add instructions of RLC opcode formatBastian Koppelmann
Add instructions of RLC opcode format. Add helper psw_write/read. Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 18:16:04 +0000