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2014-09-12exec.c: Record watchpoint fault address and directionPeter Maydell
When we check whether we've hit a watchpoint we know the address that we were attempting to access and whether it was a read or a write. Record this information in the CPUWatchpoint struct so that target-specific code can report it to the guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-09-12exec.c: Provide full set of dummy wp remove functions in user-modePeter Maydell
We already provide dummy versions of the cpu_watchpoint_insert and cpu_watchpoint_remove_all functions when CONFIG_USER_ONLY is defined. Complete the set by providing cpu_watchpoint_remove and cpu_watchpoint_remove_by_ref as well. This allows target-* code using these functions to avoid some ifdeffery. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-09-12exec.c: Relax restrictions on watchpoint length and alignmentPeter Maydell
The current implementation of watchpoints requires that they have a power of 2 length which is not greater than TARGET_PAGE_SIZE and that their address is a multiple of their length. Watchpoints on ARM don't fit these restrictions, so change the implementation so they can be relaxed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-09-12hw/arm/virt: Provide flash devices for boot ROMsPeter Maydell
Add two flash devices to the virt board, so that it can be used for running guests which want a bootrom image such as UEFI. We provide two flash devices to make it more convenient to provide both a read-only UEFI image and a read-write place to store guest-set UEFI config variables. The '-bios' command line option is set up to provide an image for the first of the two flash devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1409930126-28449-2-git-send-email-ard.biesheuvel@linaro.org
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan
Fix a single misindented line in arm_cpu_reset(). Signed-off-by: Martin Galvan <martin.galvan@tallertechnologies.com> [PMM: split this out from the previous commit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan
When calling qemu_system_reset after startup on a Cortex-M CPU, the initial values of PC, MSP and the Thumb bit weren't being set correctly if the vector table was in ROM. In particular, since Thumb was 0, a Usage Fault would arise immediately after trying to execute any instruction on a Cortex-M. Signed-off-by: Martin Galvan <martin.galvan@tallertechnologies.com> Message-id: CAOKbPbaLt-LJsAKkQdOE0cs9Xx4OWrUfpDhATXPSdtuNw2xu_A@mail.gmail.com [PMM: removed an incorrect comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12pl061: implement input interrupt logicColin Leitner
This patch adds the missing input interrupt logic to the pl061 GPIO device. To keep the floating output pins to stay high, the old state variable had to be split into two separate ones for input and output - which brings the vmstate version to 3. Edge level interrupts and I/O were tested under Linux 3.14. Level interrupt handling hasn't been tested. Signed-off-by: Colin Leitner <colin.leitner@googlemail.com> Message-id: 54024FD2.9080204@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUsDavid Hoover
Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover <spm@boiteauxlettres.sent.at> [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/virt: add linux, stdout-path to /chosen DT nodeArd Biesheuvel
Add a property "linux,stdout-path" to the /chosen DT node and make it point to the emulated UART. This allows users such as the Linux kernel to produce console output without the need to pass console= or earlycon=pl011,0x... command line arguments. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1409317439-29349-1-git-send-email-ard.biesheuvel@linaro.org Reviewed-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-console-20140905-2' ↵Peter Maydell
into staging console: pixman switchover continued, add some infrastructure to make it easier using pixman in display device emulation. # gpg: Signature made Fri 05 Sep 2014 14:38:57 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-console-20140905-2: console: Remove unused QEMU_BIG_ENDIAN_FLAG console: add qemu_pixman_linebuf_copy console: add dpy_gfx_update_dirty console: add qemu_create_displaysurface_guestmem console: stop using PixelFormat console: reimplement qemu_default_pixelformat console: add qemu_default_pixman_format console: add qemu_pixelformat_from_pixman Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-11Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140910-1' into ↵Peter Maydell
staging xhci PCIe endpoint migration compatibility fix # gpg: Signature made Wed 10 Sep 2014 06:35:20 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-usb-20140910-1: xhci PCIe endpoint migration compatibility fix Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-10xhci PCIe endpoint migration compatibility fixDr. David Alan Gilbert
Add back the PCIe config capabilities on XHCI cards in non-PCIe slots, but only for machine types before 2.1. This fixes a migration incompatibility in the XHCI PCI devices caused by: 058fdcf52cdbf57b67e7 - xhci: add endpoint cap on express bus only Note that in fixing it for compatibility with older QEMUs, it breaks compatibility with existing QEMU 2.1's on older machine types. The status before this patch was (if it used an XHCI adapter): machine type | source qemu any pre-2.1 - FAIL any 2.1... - PASS With this patch: machine type | source qemu any pre-2.1 - PASS pre-2.1 2.1... - FAIL 2.1 2.1... - PASS A test to trigger it is to add '-device nec-usb-xhci,id=xhci,addr=0x12' to the command line. Cc: qemu-stable@nongnu.org Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-09-09Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell
staging apb: implement PCI bus error interrupt map registers # gpg: Signature made Tue 09 Sep 2014 06:09:27 BST using RSA key ID AE0F321F # gpg: Can't check signature: public key not found * remotes/mcayland/tags/qemu-sparc-signed: apb: implement PCI bus error interrupt map registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-09apb: implement PCI bus error interrupt map registersMark Cave-Ayland
Both OpenBSD and FreeBSD SPARC64 attempt to read the interrupt map from the hardware and will fail if the correct ino isn't present. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-09-08Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Block pull request # gpg: Signature made Mon 08 Sep 2014 11:49:31 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: (24 commits) ide: Add resize callback to ide/core IDE: Fill the IDENTIFY request consistently vmdk: fix buf leak in vmdk_parse_extents() vmdk: fix vmdk_parse_extents() extent_file leaks ide: Add wwn support to IDE-ATAPI drive qtest/ide: Uninitialize PC allocator libqos: add a simple first-fit memory allocator MAINTAINERS: update sheepdog maintainer qemu-nbd: fix indentation and coding style qemu-nbd: add option to set detect-zeroes mode rename parse_enum_option to qapi_enum_parse and make it public block/archipelago: Use QEMU atomic builtins qemu-img: fix rebase src_cache option documentation qemu-img: clarify src_cache option documentation libqos: Added EVENT_IDX support libqos: Added MSI-X support libqos: Added test case for configuration changes in virtio-blk test libqos: Added indirect descriptor support to virtio implementation libqos: Added basic virtqueue support to virtio implementation tests: Add virtio device initialization ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-08Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' ↵Peter Maydell
into staging Patch queue for ppc - 2014-09-08 Alexander Graf (11): PPC: KVM: Fix g3beige and mac99 when HV is loaded PPC: mac99: Move NVRAM to page boundary when necessary KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd PPC: KVM: Use vm check_extension for pv hcall PPC: mac99: Fix core99 timer frequency PPC: mac_nvram: Remove unused functions PPC: mac_nvram: Allow 2 and 4 byte accesses PPC: mac_nvram: Split NVRAM into OF and OSX parts PPC: Mac: Move tbfreq into local variable PPC: Cuda: Use cuda timer to expose tbfreq to guest PPC: Fix default config ordering and add eTSEC for ppc64 Alexey Kardashevskiy (7): spapr: Move DT memory node rendering to a helper spapr: Use DT memory node rendering helper for other nodes spapr: Refactor spapr_populate_memory() to allow memoryless nodes spapr: Split memory nodes to power-of-two blocks spapr: Add a helper for node0_size calculation spapr: Fix ibm, associativity for memory nodes spapr_pci: Fix config space corruption Anton Blanchard (2): spapr-vlan: Don't touch last entry in buffer list hypervisor property clashes with hypervisor node Benjamin Herrenschmidt (2): loader: Add load_image_size() to replace load_image() spapr: Locate RTAS and device-tree based on real RMA Bharat Bhushan (4): ppc: debug stub: Get trap instruction opcode from KVM ppc: synchronize excp_vectors for injecting exception ppc: Add software breakpoint support ppc: Add hw breakpoint watchpoint support Gonglei (1): spapr: fix possible memory leak Greg Kurz (1): spapr_pci: map the MSI window in each PHB Nikunj A Dadhania (3): ppc: spapr-rtas - implement os-term rtas call spapr: add uuid/host details to device tree ppc/spapr: Fix MAX_CPUS to 255 Peter Maydell (1): hw/ppc/spapr_hcall.c: Fix typo in function names Tom Musta (20): linux-user: Fix Stack Pointer Bug in PPC setup_rt_frame linux-user: Split PPC Trampoline Encoding from Register Save linux-user: Enable Signal Handlers on PPC64 linux-user: Properly Dereference PPC64 ELFv1 Signal Handler Pointer linux-user: Implement do_setcontext for PPC64 linux-user: Handle PPC64 ELFv2 Function Pointers target-ppc: Bug Fix: rlwinm target-ppc: Bug Fix: rlwnm target-ppc: Bug Fix: rlwimi target-ppc: Bug Fix: mullwo target-ppc: Bug Fix: mullw target-ppc: Bug Fix: mulldo OV Detection target-ppc: Bug Fix: srawi target-ppc: Bug Fix: srad target-ppc: Special Case of rlwimi Should Use Deposit target-ppc: Optimize rlwinm MB=0 ME=31 target-ppc: Optimize rlwnm MB=0 ME=31 target-ppc: Clean Up mullw target-ppc: Clean up mullwo target-ppc: Implement mulldo with TCG # gpg: Signature made Mon 08 Sep 2014 11:51:15 BST using RSA key ID 03FEDC60 # gpg: Can't check signature: public key not found * remotes/agraf/tags/signed-ppc-for-upstream: (52 commits) hypervisor property clashes with hypervisor node PPC: Fix default config ordering and add eTSEC for ppc64 spapr_pci: map the MSI window in each PHB target-ppc: Implement mulldo with TCG target-ppc: Clean up mullwo target-ppc: Clean Up mullw target-ppc: Optimize rlwnm MB=0 ME=31 target-ppc: Optimize rlwinm MB=0 ME=31 target-ppc: Special Case of rlwimi Should Use Deposit spapr-vlan: Don't touch last entry in buffer list spapr_pci: Fix config space corruption PPC: Cuda: Use cuda timer to expose tbfreq to guest PPC: Mac: Move tbfreq into local variable PPC: mac_nvram: Split NVRAM into OF and OSX parts PPC: mac_nvram: Allow 2 and 4 byte accesses PPC: mac_nvram: Remove unused functions PPC: mac99: Fix core99 timer frequency PPC: KVM: Use vm check_extension for pv hcall KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd target-ppc: Bug Fix: srad ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-08hypervisor property clashes with hypervisor nodeAnton Blanchard
dtc fails on a recent QEMU snapshot: ERROR (name_properties): "name" property in /hypervisor#1 is incorrect ("hypervisor" instead of base node name) Looking at the device tree we have a hypervisor property: # lsprop hypervisor hypervisor "kvm" But we also have a hypervisor node, with a name that doesn't match: # lsprop hypervisor#1/ name "hypervisor" compatible "linux,kvm" linux,phandle 7e5eb5d8 (2120136152) Commit c08ce91d309c (spapr: add uuid/host details to device tree) looks to have collided with an earlier patch. Remove the hypervisor property. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: Fix default config ordering and add eTSEC for ppc64Alexander Graf
We messed up the ordering in our default configs for PPC. The top entries are generic entries, then come sections that indicate that features are only in because of a special feature (such as PReP). Fix the ordering again and while at it add eTSEC support to the ppc64 target so that we can spawn eTSEC adapters with qemu-system-ppc64. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08spapr_pci: map the MSI window in each PHBGreg Kurz
On sPAPR, virtio devices are connected to the PCI bus and use MSI-X. Commit cc943c36faa192cd4b32af8fe5edb31894017d35 has modified MSI-X so that writes are made using the bus master address space and follow the IOMMU path. Unfortunately, the IOMMU address space address space does not have an MSI window: the notification is silently dropped in unassigned_mem_write instead of reaching the guest... The most visible effect is that all virtio devices are non-functional on sPAPR since then. :( This patch does the following: 1) map the MSI window into the IOMMU address space for each PHB - since each PHB instantiates its own IOMMU address space, we can safely map the window at a fixed address (SPAPR_PCI_MSI_WINDOW) - no real need to keep the MSI window setup in a separate function, the spapr_pci_msi_init() code moves to spapr_phb_realize(). 2) kill the global MSI window as it is not needed in the end Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Implement mulldo with TCGTom Musta
Optimize mulldo by using the muls2_i64 operation rather than a helper. Eliminate the obsolete helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Clean up mullwoTom Musta
Simplify the implementation of mullwo. For 64 bit CPUs, the result is the concatenation of the upper and lower parts of the muls2_i32 operation, which may be slightly better than deposit. For 32 bit CPUs, the lower part of the muls_i32 operation is moved into the target GPR. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Clean Up mullwTom Musta
Eliminate the unecessary ext32s TCG operation and make the multiplication operation explicitly 32 bit. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta
Optimize the special case of rlwnm where MB=0 and ME=31. This can be implemented using a ROTL. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta
Optimize the special case of rlwinm where MB=0 and ME=31. This can be implemented as a 32-bit ROTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Special Case of rlwimi Should Use DepositTom Musta
The special case of rlwimi where MB <= ME and SH = 31-ME can be implemented with a single TCG deposit operation. This replaces the less general case of SH = MB = 0 and ME = 31. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08spapr-vlan: Don't touch last entry in buffer listAnton Blanchard
The last 8 bytes of the buffer list is defined to contain the number of dropped frames. At the moment we use it to store rx entries, which trips up ethtool -S: rx_no_buffer: 9223380832981355136 Fix this by skipping the last buffer list entry. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08spapr_pci: Fix config space corruptionAlexey Kardashevskiy
When disabling MSI/MSIX via "ibm,change-msi" RTAS call, no check was made if MSI or MSIX is actually supported and the MSI message was reset unconditionally. If this happened on a device which does not support MSI (but does support MSIX, otherwise "ibm,change-msi" would not be called), this device would have PCIDevice::msi_cap field (MSI capability offset) set to zero and writing a vector would actually clear PCI status. This clears MSI message only if MSI or MSIX is present on a device. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: Cuda: Use cuda timer to expose tbfreq to guestAlexander Graf
Mac OS X calibrates a number of frequencies on bootup based on reading tb values on bootup and comparing them to via cuda timer values. The only variable we can really steer well (thanks to KVM) is the cuda frequency. So let's use that one to fake Mac OS X into believing the bus frequency is tbfreq * 4. That way Mac OS X will automatically calculate the correct timebase frequency. With this patch and the patch set I posted earlier I can successfully run Mac OS X 10.2, 10.3 and 10.4 guests with -M mac99 on TCG and KVM. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: Mac: Move tbfreq into local variableAlexander Graf
We already expose the real CPU's tb frequency to the guest via fw_cfg. Soon we will need to also expose it to the MacIO, so let's move it to a variable that we can leverage every time we need the frequency. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: mac_nvram: Split NVRAM into OF and OSX partsAlexander Graf
Mac OS X (at least with -M mac99) searches for a valid NVRAM partition of a special Apple type. If it can't find that partition in the first half of NVRAM, it will look at the second half. There are a few implications from this. The first is that we need to split NVRAM into 2 halves - one for Open Firmware use, the other one for Mac OS X. Without this split Mac OS X will just loop endlessly over the second half trying to find a partition. The other implication is that we should provide a specially crafted Mac OS X compatible NVRAM partition on the second half that Mac OS X can happily use as it sees fit. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: mac_nvram: Allow 2 and 4 byte accessesAlexander Graf
The NVRAM in our Core99 machine really supports 2byte and 4byte accesses just as well as 1byte accesses. In fact, Mac OS X uses those. Add support for higher register size granularities. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: mac_nvram: Remove unused functionsAlexander Graf
The macio_nvram_read and macio_nvram_write functions are never called, just remove them. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: mac99: Fix core99 timer frequencyAlexander Graf
There is a special timer in the mac99 machine that we recently started to emulate. Unfortunately we emulated it in the wrong frequency. This patch adapts the frequency Mac OS X uses to evaluate results from this timer, making calculations it bases off of it work. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08PPC: KVM: Use vm check_extension for pv hcallAlexander Graf
To find out whether we support the KVM hypercall interface we need to ask KVM on the VM level rather than the global KVM level, because Book3S HV KVM does not support it and we play conservative when both HV and PR are loaded. So instead, use the VM helper that falls back to global KVM enumeration. That should cover all cases. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08KVM: Add helper to run KVM_CHECK_EXTENSION on vm fdAlexander Graf
We now can call KVM_CHECK_EXTENSION on the kvm fd or on the vm fd, whereas the vm version is more accurate when it comes to PPC KVM. Add a helper to make the vm version available that falls back to the non-vm variant if the vm one is not available yet to stay compatible. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: sradTom Musta
Fix the check for carry in the srad helper to properly construct the mask -- a "1ULL" must be used (instead of "1") in order to get the desired result. Example: R3 8000000000000000 R4 F3511AD4A2CD4C38 srad 3,3,4 Should *not* set XER[CA] but does without this patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: srawiTom Musta
For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: mulldo OV DetectionTom Musta
Fix the code to properly detect overflow; the 128 bit signed product must have all zeroes or all ones in the first 65 bits otherwise OV should be set. Example: R3 45F086A5D5887509 R4 0000000000000002 mulldo 3,3,4 Should set XER[OV]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: mullwTom Musta
For 64-bit implementations, the mullw result is the 64 bit product of the sign-extended least significant 32 bits of the source registers. Fix the code to properly sign extend the source operands and produce a 64 bit product. Example: R3 00000000002F37A0 R4 41C33D242F816715 mullw 3,3,4 R3 expected : 0008C3146AE0F020 R3 actual : 000000006AE0F020 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: mullwoTom Musta
On 64-bit implementations, the mullwo result is the 64 bit product of the signed 32 bit operands. Fix the implementation to properly deposit the upper 32 bits into the target register. Example: R3 0407DED115077586 R4 53778DF3CA992E09 mullwo 3,3,4 R3 expected : FB9D02730D7735B6 R3 actual : 000000000D7735B6 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwimiTom Musta
The rlwimi specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Also fix the special case of MB=31 and ME=0 to copy the entire contents of the source GPR. Examples: R3 FFFFFFFFFFFFFFF0 rlwimi 3,3,29,14,1 R3 expected : 1FFFFFFE3FFFFFFE R3 actual : 000000003FFFFFFE (without this patch) R3 ED7EB4DD824F0853 rlwimi 3,3,10,31,0 R3 expected : 3C214E09024F0853 R3 actual : 00000000024F0853 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwnmTom Musta
The rlwnm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = 0000000000000002 R4 = 7FFFFFFFFFFFFFFF rlwnm 3,3,4,31,16 R3 expected : 0000000100000001 R3 actual : 0000000000000001 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08target-ppc: Bug Fix: rlwinmTom Musta
The rlwinm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = F7487D82EC6F75DF rlwinm 3,3,5,12,4 R3 expected : 8DEEBBFD880EBBFD R3 actual : 00000000880EBBFD (without this fix) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08ppc/spapr: Fix MAX_CPUS to 255Nikunj A Dadhania
MAX_CPUS 256 is inconsistent with qemu supporting upto 255 cpus. This MAX_CPUS number was percolated back to "virsh capabilities" with wrong max_cpus. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08ppc: Add hw breakpoint watchpoint supportBharat Bhushan
This patch adds hardware breakpoint and hardware watchpoint support for ppc. On BOOKE architecture we cannot share debug resources between QEMU and guest because: When QEMU is using debug resources then debug exception must be always enabled. To achieve this we set MSR_DE and also set MSRP_DEP so guest cannot change MSR_DE. When emulating debug resource for guest we want guest to control MSR_DE (enable/disable debug interrupt on need). So above mentioned two configuration cannot be supported at the same time. So the result is that we cannot share debug resources between QEMU and Guest on BOOKE architecture. In the current design QEMU gets priority over guest, this means that if QEMU is using debug resources then guest cannot use them and if guest is using debug resource then qemu can overwrite them. When QEMU is not able to handle debug exception then we inject program exception to guest. Yes program exception NOT debug exception and the reason is: 1) QEMU and guest not sharing debug resources 2) For software breakpoint QEMU uses a ehpriv-1 instruction; So there cannot be any reason that we are in qemu with exit reason KVM_EXIT_DEBUG for guest set debug exception, only possibility is guest executed ehpriv-1 privilege instruction and that's why we are injecting program exception. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08ppc: Add software breakpoint supportBharat Bhushan
This patch allow insert/remove software breakpoint. When QEMU is not able to handle debug exception then we inject program exception to guest because for software breakpoint QEMU uses a ehpriv-1 instruction; So there cannot be any reason that we are in qemu with exit reason KVM_EXIT_DEBUG for guest set debug exception, only possibility is guest executed ehpriv-1 privilege instruction and that's why we are injecting program exception. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> [agraf: make deflect comment booke/book3s agnostic] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08ppc: synchronize excp_vectors for injecting exceptionBharat Bhushan
This patch synchronizes env->excp_vectors[] with env->iovr[]. This is required for using the existing interrupt injection mechanism for kvm. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08ppc: debug stub: Get trap instruction opcode from KVMBharat Bhushan
Get trap instruction opcode from KVM and this opcode will be used for setting software breakpoint in following patch Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08spapr: Locate RTAS and device-tree based on real RMABenjamin Herrenschmidt
We currently calculate the final RTAS and FDT location based on the early estimate of the RMA size, cropped to 256M on KVM since we only know the real RMA size at reset time which happens much later in the boot process. This means the FDT and RTAS end up right below 256M while they could be much higher, using precious RMA space and limiting what the OS bootloader can put there which has proved to be a problem with some OSes (such as when using very large initrd's) Fortunately, we do the actual copy of the device-tree into guest memory much later, during reset, late enough to be able to do it using the final RMA value, we just need to move the calculation to the right place. However, RTAS is still loaded too early, so we change the code to load the tiny blob into qemu memory early on, and then copy it into guest memory at reset time. It's small enough that the memory usage doesn't matter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: fixed errors from checkpatch.pl, defined RTAS_MAX_ADDR] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-09-08loader: Add load_image_size() to replace load_image()Benjamin Herrenschmidt
A subsequent patch to ppc/spapr needs to load the RTAS blob into qemu memory rather than target memory (so it can later be copied into the right spot at machine reset time). I would use load_image() but it is marked deprecated because it doesn't take a buffer size as argument, so let's add load_image_size() that does. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: fixed errors from checkpatch.pl] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
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