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2017-04-29slirp: VMStatify socket levelDr. David Alan Gilbert
Working up the stack, this replaces the slirp_socket_load/save with VMState definitions. A place holder for IPv6 support is added as a comment; it needs testing once the rest of the IPv6 code is there. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: Common lhost/fhost unionDr. David Alan Gilbert
The socket structure has a pair of unions for lhost and fhost addresses; the unions are identical so split them out into a separate union declaration. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: VMStatify sbufDr. David Alan Gilbert
Convert the sbuf structure to a VMStateDescription. Note this uses the VMSTATE_WITH_TMP mechanism to calculate and reload the offsets based on the pointers. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: VMState conversion; tcpcbDr. David Alan Gilbert
Convert the migration of the struct tcpcb to use a VMStateDescription, the rest of it will come later. Mostly mechanical, except for conversion of some 'char' to uint8_t to ensure portability. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: fix pinging the virtual ipv4 DNS serverSamuel Thibault
so that people do not think it is not working at least basically. Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: tftp, copy sockaddr_sizeMarc-André Lureau
ASAN detects an "unknown-crash" when running pxe-test: /ppc64/pxe/spapr-vlan: ================================================================= ==7143==ERROR: AddressSanitizer: unknown-crash on address 0x7f6dcd298d30 at pc 0x55e22218830d bp 0x7f6dcd2989e0 sp 0x7f6dcd2989d0 READ of size 128 at 0x7f6dcd298d30 thread T2 #0 0x55e22218830c in tftp_session_allocate /home/elmarco/src/qq/slirp/tftp.c:73 #1 0x55e22218a1f8 in tftp_handle_rrq /home/elmarco/src/qq/slirp/tftp.c:289 #2 0x55e22218b54c in tftp_input /home/elmarco/src/qq/slirp/tftp.c:446 #3 0x55e2221833fe in udp6_input /home/elmarco/src/qq/slirp/udp6.c:82 #4 0x55e222137b17 in ip6_input /home/elmarco/src/qq/slirp/ip6_input.c:67 Address 0x7f6dcd298d30 is located in stack of thread T2 at offset 96 in frame #0 0x55e222182420 in udp6_input /home/elmarco/src/qq/slirp/udp6.c:13 This frame has 3 object(s): [32, 48) '<unknown>' [96, 124) 'lhost' <== Memory access at offset 96 partially overflows this variable [160, 200) 'save_ip' <== Memory access at offset 96 partially underflows this variable The sockaddr_storage pointer is the sockaddr_in6 lhost on the stack. Copy only the source addr size. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp/smb: Replace constant strings by glib stringDr. David Alan Gilbert
gcc 7 (on fedora 26) objects to many of the snprintf's in the smb path and command creation because it can't figure out that the smb_dir (i.e. the /tmp dir for the configuration) is known to be short. Replace all these fixed length buffers by g_str* functions that dynamically allocate and use g_dir_make_tmp to make the directory. (It's fairly new glib but we have a compat function for it). Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-29slirp: allow host port 0 for hostfwdVincent Bernat
The OS will allocate automatically a free port. This is useful if you want to be sure to not get any port conflict. You still have to figure out which port you got, for example with "lsof" (this could be exposed in the monitor if needed). Example of use: $ qemu-system-x86_64 -net user,hostfwd=127.0.0.1:0-:22 ... Then, get your port with: $ lsof -np 1474 | grep LISTEN qemu-syst 31777 bernat 12u IPv4 [...] TCP 127.0.0.1:35145 (LISTEN) Signed-off-by: Vincent Bernat <vincent@bernat.im> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2017-04-26Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170426' into stagingPeter Maydell
Fix for exit_atomic tcg opcode paths # gpg: Signature made Wed 26 Apr 2017 18:27:11 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170426: tcg: Initialize return value after exit_atomic Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-26tcg: Initialize return value after exit_atomicRichard Henderson
Users of tcg_gen_atomic_cmpxchg and do_atomic_op rightfully utilize the output. Even though this code is dead, it gets translated, and without the initialization we encounter a tcg_error. Reported-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Tested-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-04-26Revert "COLO-compare: Optimize tcp compare trace event"Peter Maydell
This reverts commit 0fc8aec7de64f2bf83a274a2a38b938ce03425d2. In commit 2dfe5113b11 we split a trace event with a lot of arguments in two, because the UST trace backend has a limit on the number of arguments you can have in a single trace event. Unfortunately we subsequently forgot about this, and in commit 0fc8aec7de64f2 we merged the two trace events again, recreating the "UST backend doesn't build" bug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-26Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20170426' into ↵Peter Maydell
staging HMP pull, with tcg fix # gpg: Signature made Wed 26 Apr 2017 14:55:30 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-hmp-20170426: tests: Add a tester for HMP commands libqtest: Add a generic function to run a callback function for every machine libqtest: Ignore QMP events when parsing the response for HMP commands monitor: Check whether TCG is enabled before running the "info jit" code hmp: gpa2hva and gpa2hpa hostaddr command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-26tests: Add a tester for HMP commandsThomas Huth
HMP commands do not get any automatic testing yet, so on certain QEMU machines, some HMP commands were causing crashes in the past. Thus we should test HMP commands in our test suite, too, to avoid that such problems creep in again in the future. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1493097407-20482-1-git-send-email-thuth@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-04-26libqtest: Add a generic function to run a callback function for every machineThomas Huth
Some tests need to run single tests for every available machine of the current QEMU binary. To avoid code duplication, let's extract this code that deals with 'query-machines' into a separate function. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1490860207-8302-3-git-send-email-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-04-26libqtest: Ignore QMP events when parsing the response for HMP commandsThomas Huth
When running certain HMP commands (like "device_del") via QMP, we can sometimes get a QMP event in the response first, so that the "g_assert(ret)" statement in qtest_hmp() triggers and the test fails. Fix this by ignoring such QMP events while looking for the real return value from QMP. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1490860207-8302-2-git-send-email-thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Added note to qtest_hmp/qtest_hmpv's header description to say it discards events
2017-04-26monitor: Check whether TCG is enabled before running the "info jit" codeThomas Huth
The "info jit" command currently aborts on Mac OS X with the message "qemu_mutex_lock: Invalid argument" when running with "-M accel=qtest". We should only call into the TCG code here if TCG has really been enabled and initialized. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1493179907-22516-1-git-send-email-thuth@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-04-26hmp: gpa2hva and gpa2hpa hostaddr commandPaolo Bonzini
These commands are useful when testing machine-check passthrough. gpa2hva is useful to inject a MADV_HWPOISON madvise from gdb, while gpa2hpa is useful to inject an error with the mce-inject kernel module. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1490021158-4469-1-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20170420133058.12911-1-pbonzini@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-04-26Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.10-20170426' ↵Peter Maydell
into staging ppc patch queue 2017-04-26 Here's a respind of my first pull request for qemu-2.10, consisting of assorted patches which have accumulated while qemu-2.9 stabilized. Highlights are: * Rework / cleanup of the XICS interrupt controller * Substantial improvement to the 'powernv' machine type - Includes an MMIO XICS version * POWER9 support improvements - POWER9 guests with KVM - Partial support for POWER9 guests with TCG * IOMMU and VFIO improvements * Assorted minor changes There are several IPMI patches here that aren't usually in my area of maintenance, but there isn't a regular maintainer and these patches are for the benefit of the powernv machine type. This pull request supersedes my 2017-04-26 pull request. This new set fixes a bug in one of the aforementioned IPMI patches which caused clang sanitizer failures (and may have crashed on some libc / host versions). # gpg: Signature made Wed 26 Apr 2017 07:58:10 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.10-20170426: (48 commits) MAINTAINERS: Remove myself from e500 target/ppc: Style fixes e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read target/ppc: Flush TLB on write to PIDR spapr-cpu-core: Release ICPState object during CPU unrealization ppc/pnv: generate an OEM SEL event on shutdown ppc/pnv: add initial IPMI sensors for the BMC simulator ppc/pnv: populate device tree for IPMI BT devices ppc/pnv: populate device tree for serial devices ppc/pnv: populate device tree for RTC devices ppc/pnv: scan ISA bus to populate device tree ppc/pnv: enable only one LPC bus ppc/pnv: Add support for POWER8+ LPC Controller spapr: remove the 'nr_servers' field from the machine target/ppc: Fix size of struct PPCElfPrstatus ipmi: introduce an ipmi_bmc_gen_event() API ipmi: introduce an ipmi_bmc_sdr_find() API ipmi: provide support for FRUs ipmi: use a file to load SDRs ppc: add IPMI support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-26Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20170421-v2-tag' ↵Peter Maydell
into staging Xen 2017/04/21 + fix # gpg: Signature made Tue 25 Apr 2017 19:10:37 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # gpg: aka "Stefano Stabellini <sstabellini@kernel.org>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20170421-v2-tag: (21 commits) move xen-mapcache.c to hw/i386/xen/ move xen-hvm.c to hw/i386/xen/ move xen-common.c to hw/xen/ add xen-9p-backend to MAINTAINERS under Xen xen/9pfs: build and register Xen 9pfs backend xen/9pfs: send responses back to the frontend xen/9pfs: implement in/out_iov_from_pdu and vmarshal/vunmarshal xen/9pfs: receive requests from the frontend xen/9pfs: connect to the frontend xen/9pfs: introduce Xen 9pfs backend 9p: introduce a type for the 9p header xen: import ring.h from xen configure: use pkg-config for obtaining xen version xen: additionally restrict xenforeignmemory operations xen: use libxendevice model to restrict operations xen: use 5 digit xen versions xen: use libxendevicemodel when available configure: detect presence of libxendevicemodel xen: create wrappers for all other uses of xc_hvm_XXX() functions xen: rename xen_modified_memory() to xen_hvm_modified_memory() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-26MAINTAINERS: Remove myself from e500Scott Wood
I recently left Freescale/NXP, and even before that it'd been a few years since I was actively involved in KVM/QEMU work. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26target/ppc: Style fixesDavid Gibson
This makes a small step fixing one of many style problems that exist in the older ppc code. This removes spaces between function (or macro) name and the following '('. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user readBernhard Kaindl
This patch registers mfspr 259 for Book3S and e500 family cores following this research: mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to: - PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20) - IBM PowerPC 970MP RISC Microprocessor User's Manual v2.1, page 48 - Amit Singh: "Mac OS X Internals: A Systems Approach" on 970 and 970FX cores: He demonstrates mfspr 259 reading TLS data from Mac OS X on G5 on page 588 - NXP documents it in the Core Reference Manuals of: e500, e500mc and e5500 - getcpu() of the 32 & 64-bit Book3S Linux vDSOs use it to read the core number mfspr 259 does not appear to be implemented in these cores according to: - 74xx series: MPC7410/MPC7400 and MPC7450 RISC Microprocessor Reference Manuals - 4xx series: PPC440 Processor User's Manual, Revision 1.09 by AMCC - 750 series: IBM PowerPC 750CL RISC Microprocessor User's Manual - e200 series: e200z4 Power Architectureâ Core Reference Manual Implementation: gen_spr_usprg3() is called from init_proc_book3s_common() (covers the 970 and POWER cores) and init_proc_e500() (covers the e500 family) to register spr_read_ureg() in the same way which it already provides the mapped SPR access for SPR_USPRG4-7 in gen_spr_usprgh() for cores which have the same read-only mapped SPRG register access for SPRG4-7. Verified using Linux by pinning a thread to a core and checking sched_getcpu() using qemu-system-ppc64 -M pseries -cpu POWER8 using MTTCG on a x86_64 host. Signed-off-by: Bernhard Kaindl <bernhard.kaindl@thalesgroup.com> Reviewed-by: Stefan Resch <stefan.resch@thalesgroup.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26target/ppc: Flush TLB on write to PIDRSuraj Jitindar Singh
The PIDR (process id register) is used to store the id of the currently running process, which is used to select the process table entry used to perform address translation. This means that when we write to this register all the translations in the TLB become outdated as they are for a previously running process. Thus when this register is written to we need to invalidate the TLB entries to ensure stale entries aren't used to to perform translation for the new process, which would result in at best segfaults or alternatively just random memory being accessed. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Fixed compile error for 32-bit targets] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26spapr-cpu-core: Release ICPState object during CPU unrealizationBharata B Rao
Recent commits that re-organized ICPState object missed to destroy the object when CPU is unrealized. Fix this so that CPU unplug doesn't abort QEMU. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: generate an OEM SEL event on shutdownCédric Le Goater
OpenPOWER systems expect to be notified with such an event before a shutdown or a reboot. An OEM SEL message is sent with specific identifiers and a user data containing the request : OFF or REBOOT. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: add initial IPMI sensors for the BMC simulatorCédric Le Goater
Skiboot, the firmware for the PowerNV platform, expects the BMC to provide some specific IPMI sensors. These sensors are exposed in the device tree and their values are updated by the firmware at boot time. Sensors of interest are : "FW Boot Progress" "Boot Count" As such a device is defined on the command line, we can only detect its presence at reset time. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: populate device tree for IPMI BT devicesCédric Le Goater
When an ipmi-bt device [1] is defined on the ISA bus, we need to populate the device tree with the object properties. Such devices are created with the command line options : -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10 [1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg03168.html Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: populate device tree for serial devicesCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: populate device tree for RTC devicesCédric Le Goater
The code could be common to any ISA device but we are missing the IO length. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: scan ISA bus to populate device treeCédric Le Goater
This is an empty shell that we will use to include nodes in the device tree for ISA devices. We expect RTC, UART and IPMI BT devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: enable only one LPC busCédric Le Goater
The default LPC bus of a multichip system is on chip 0. It's recognized by the firmware (skiboot) using a "primary" property in the device tree. We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of a chip and set the property directly from the machine level. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: Add support for POWER8+ LPC ControllerBenjamin Herrenschmidt
It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26spapr: remove the 'nr_servers' field from the machineCédric Le Goater
xics_system_init() does not need 'nr_servers' anymore as it is only used to define the 'interrupt-controller' node in the device tree. So let's just compute the value when calling spapr_dt_xics(). This also gives us an opportunity to simplify the xics_system_init() routine and introduce a specific spapr_ics_create() helper to create the sPAPR ICS object. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26target/ppc: Fix size of struct PPCElfPrstatusAnton Blanchard
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus is the wrong size. Fix it. Signed-off-by: Anton Blanchard <anton@samba.org> Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support") Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ipmi: introduce an ipmi_bmc_gen_event() APICédric Le Goater
It will be used to fill the message buffer with custom events expected by some systems. Typically, an Open PowerNV platform guest is notified with an OEM SEL message before a shutdown or a reboot. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ipmi: introduce an ipmi_bmc_sdr_find() APICédric Le Goater
This patch exposes a new IPMI routine to query a sdr entry from the sdr table maintained by the IPMI BMC simulator. The API is very similar to the internal sdr_find_entry() routine and should be used the same way to query one or all sdrs. A typical use would be to loop on the sdrs to build nodes of a device tree. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ipmi: provide support for FRUsCédric Le Goater
This patch provides a simple FRU support for the BMC simulator. FRUs are loaded from a file which name is specified in the object properties, each entry having a fixed size, also specified in the properties. If the file is unknown or not accessible for some reason, a unique entry of 1024 bytes is created as a default. Just enough to start some simulation. These commands complies with the IPMI spec : "34. FRU Inventory Device Commands". Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Corey Minyard <cminyard@mvista.com> [dwg: Folded in subsequent fix to handle NULL filename] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ipmi: use a file to load SDRsCédric Le Goater
The IPMI BMC simulator populates the sdr/sensor tables with a minimal set of entries (Watchdog). But some qemu platforms might want to use extra entries for their custom needs. This patch modifies slighty the initializing routine to take into account a larger set read from a file. The name of the file to use is defined through a new 'sdr' property of the simulator device. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc: add IPMI supportCédric Le Goater
OpenPOWER systems use a BT device to communicate with the BMC. Provide support for it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: Add OCC model stub with interrupt supportBenjamin Herrenschmidt
The OCC is an on-chip microcontroller based on a ppc405 core used for various power management tasks. It comes with a pile of additional hardware sitting on the PIB (aka XSCOM bus). At this point we don't emulate it (nor plan to do so). However there is one facility which is provided by the surrounding hardware that we do need, which is the interrupt generation facility. OPAL uses it to send itself interrupts under some circumstances and there are other uses around the corner. So this implement just enough to support this. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: - updated for qemu-2.9 - changed the XSCOM interface to fit new model - QOMified the model ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: Add cut down PSI bridge model and hookup external interruptCédric Le Goater
The Processor Service Interface (PSI) Controller is one of the engines of the "Bridge" unit which connects the different interfaces to the Power Processor. This adds just enough of the PSI bridge to handle various on-chip and the one external interrupt. The rest of PSI has to do with the link to the IBM FSP service processor which we don't plan to emulate (not used on OpenPower machines). The ics_get() and ics_resend() handlers of the XICSFabric interface of the PowerNV machine are now defined to handle the Interrupt Control Source of PSI. The InterruptStatsProvider interface is also modified to dump the new ICS. Originally from Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: add memory regions for the ICP registersCédric Le Goater
This provides to a PowerNV chip (POWER8) access to the Interrupt Management area, which contains the registers of the Interrupt Control Presenters of each thread. These are used to accept, return, forward interrupts in the system. This area is modeled with a per-chip container memory region holding all the ICP registers. Each thread of a chip is then associated with its ICP registers using a memory subregion indexed by its PIR number in the overall region. The device tree is populated accordingly. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: add a helper to calculate MMIO addresses registersCédric Le Goater
Some controllers (ICP, PSI) have a base register address which is calculated using the chip id. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: create the ICP object under PnvCoreCédric Le Goater
Each thread of a core is linked to an ICP. This allocates a PnvICPState object before the PowerPCCPU object is realized and lets the XICSFabric do the store under the 'intc' backlink when xics_cpu_setup() is called. This modeling removes the need of maintaining an array of ICP objects under the PowerNV machine and also simplifies the XICSFabric icp_get() handler. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: extend the machine with a InterruptStatsProvider interfaceCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: extend the machine with a XICSFabric interfaceCédric Le Goater
A XICSFabric QOM interface is used by the XICS layer to manipulate the ICP and ICS objects. Let's define the associated handlers for the PowerNV machine. All handlers should be defined even if there is no ICS under the PowerNV machine yet. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/pnv: add a PnvICPState objectCédric Le Goater
This provides a new ICPState object for the PowerNV machine (POWER8). Access to the Interrupt Management area is done though a memory region. It contains the registers of the Interrupt Control Presenters of each thread which are used to accept, return, forward interrupts in the system. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26ppc/xics: add a realize() handler to ICPStateClassCédric Le Goater
It will be used by derived classes in PowerNV for customization. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26spapr: allocate the ICPState object from under sPAPRCPUCoreCédric Le Goater
Today, all the ICPs are created before the CPUs, stored in an array under the sPAPR machine and linked to the CPU when the core threads are realized. This modeling brings some complexity when a lookup in the array is required and it can be simplified by allocating the ICPs when the CPUs are. This is the purpose of this proposal which introduces a new 'icp_type' field under the machine and creates the ICP objects of the right type (KVM or not) before the PowerPCCPU object are. This change allows more cleanups : the removal of the icps array under the sPAPR machine and the removal of the xics_get_cpu_index_by_dt_id() helper. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-04-26spapr: move the IRQ server number mapping under the machineCédric Le Goater
This is the second step to abstract the IRQ 'server' number of the XICS layer. Now that the prereq cleanups have been done in the previous patch, we can move down the 'cpu_dt_id' to 'cpu_index' mapping in the sPAPR machine handler. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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