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2014-10-24MAINTAINERS: add myself as MIPS guest cores co-maintainerLeon Alrae
Add myself to the maintainer list for MIPS guest cores and update the status from "Odd Fixes" to "Maintained". Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 1413459487-13658-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1413982829-27225-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20141024' into staging target-arm queue: * remove pointless 'info pcmcia' and a lot of now-dead code * register ARM cpu reset handlers even if not using -kernel * update to libvixl 1.6 * various minor code cleanups * support PSCI under TCG ('virt' machine can now be shut down, SMP configurations work) * correct the sense of the AArch64 DCZID DZP bit * report a valid L1Ip field in CTR_EL0 for CPU type "any" * correctly UNDEF writes to FPINST/FPINST2 from EL0 * more preparatory code refactoring for EL2/EL3 support # gpg: Signature made Fri 24 Oct 2014 12:35:52 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20141024: (23 commits) target-arm: A32: Emulate the SMC instruction target-arm: make arm_current_el() return EL3 target-arm: rename arm_current_pl to arm_current_el target-arm: reject switching to monitor mode target-arm: add arm_is_secure() function target-arm: increase arrays of registers R13 & R14 target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" target-arm: Correct sense of the DCZID DZP bit arm/virt: enable PSCI emulation support for system emulation target-arm: add emulation of PSCI calls for system emulation target-arm: Add support for A32 and T32 HVC and SMC insns target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers target-arm: add missing PSCI constants needed for PSCI emulation target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes target-arm: add powered off cpu state omap_gpmc.c: Remove duplicate assignment disas/libvixl/a64/instructions-a64.h: Remove unused constants arm_gic: remove unused parameter. disas/libvixl: Update to libvixl 1.6 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler
Implements SMC instruction in AArch32 using the A32 syndrome. When executing SMC instruction from monitor CPU mode SCR.NS bit is reset. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1413910544-20150-7-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler
Make arm_current_el() return EL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly inferred from arm_ current_el(). Change assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
Renamed the arm_current_pl CPU function to more accurately represent that it returns the ARMv8 EL rather than ARMv7 PL. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-5-git-send-email-greg.bellows@linaro.org [PMM: fixed a minor merge resolution error in a couple of hunks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov
Reject switching to monitor mode from non-secure state. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler
arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell
The ARM ARM requires that the FPINST and FPINST2 VFP control registers are not accessible to code at EL0. We were already correctly implementing this for reads of these registers; add the missing check for the write code path. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412967447-20931-1-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell
For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell
The DZP bit in the DCZID system register should be set if the control bits which prohibit use of the DC ZVA instruction have been set (it stands for Data Zero Prohibited). However we had the sense of the test inverted; fix this so that the bit reads correctly. To avoid this regressing the behaviour of the user-mode emulator, we must set the DZE bit in the SCTLR for that config so that userspace continues to see DZP as zero (it was getting the correct result by accident previously). Reported-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christopher Covington <cov@codeaurora.org> Message-id: 1412959792-20708-1-git-send-email-peter.maydell@linaro.org
2014-10-24arm/virt: enable PSCI emulation support for system emulationRob Herring
Now that we have PSCI emulation, enable it for the virt platform. This simplifies the virt machine a bit now that PSCI no longer needs to be a KVM only feature. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-8-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring
Add support for handling PSCI calls in system emulation. Both version 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support by setting the "psci-conduit" QOM property on the cpus to SMC or HVC emulation and having a PSCI binding in their dtb. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-7-git-send-email-peter.maydell@linaro.org [PMM: made system reset/off PSCI functions power down the CPU so we obey the PSCI API requirement never to return from them; rearranged how the code is plumbed into the exception system, so that we split "is this a valid call?" from "do the call"] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell
Add support for HVC and SMC instructions to the A32 and T32 decoder. Using these for real exceptions to EL2 or EL3 is currently not supported (the do_interrupt routine does not handle them) but we require the instruction support to implement PSCI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-6-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell
SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs if EL2 is not implemented. Move the handling of this from translate-a64.c into the pre_smc and pre_hvc helper functions. This is necessary because use of these instructions for PSCI takes precedence over this UNDEF case, and we can't tell if this is a PSCI call until runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-5-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add missing PSCI constants needed for PSCI emulationArd Biesheuvel
This adds some PSCI function IDs and symbolic return codes that are needed to implement PSCI emulation in TCG mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-4-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring
User mode emulation should never get interrupts and thus should not use the system emulation exception handler function. Remove the reference, and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add system mode only functionality to it. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-3-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add powered off cpu stateRob Herring
Add tracking of cpu power state in order to support powering off of cores in system emuluation. The initial state is determined by the start-powered-off QOM property. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-2-git-send-email-peter.maydell@linaro.org
2014-10-24omap_gpmc.c: Remove duplicate assignmentDr. David Alan Gilbert
This looks like an old merge error and should have no effect. (Build tested only) Found by Coccinelle using Julia Lawall's script: https://lkml.org/lkml/2014/8/23/128 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1414055855-6688-1-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24disas/libvixl/a64/instructions-a64.h: Remove unused constantsChen Gang
The instructions-a64.h header defines a number of floating point constants whose initializers are function calls. gcc 5 will warn if these constants are not used by the C or C++ file which includes the header, because they imply a runtime cost. Since for the files QEMU uses from libvixl we don't use these constants at all, just remove them. Upstream intend to fix these by shifting to an 'extern const' in the header plus definition in a suitable source file, so we can drop this patch when we sync with the upcoming libvixl 1.7. The related compiling error: CXX disas/arm-a64.o In file included from /upstream/qemu/disas/libvixl/a64/disasm-a64.h:32:0, from disas/arm-a64.cc:20: disas/libvixl/a64/instructions-a64.h:98:13: error: 'vixl::kFP32PositiveInfinity' defined but not used [-Werror=unused-variable] const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000); ^ disas/libvixl/a64/instructions-a64.h:99:13: error: 'vixl::kFP32NegativeInfinity' defined but not used [-Werror=unused-variable] const float kFP32NegativeInfinity = rawbits_to_float(0xff800000); ^ disas/libvixl/a64/instructions-a64.h:100:14: error: 'vixl::kFP64PositiveInfinity' defined but not used [-Werror=unused-variable] const double kFP64PositiveInfinity = ^ disas/libvixl/a64/instructions-a64.h:102:14: error: 'vixl::kFP64NegativeInfinity' defined but not used [-Werror=unused-variable] const double kFP64NegativeInfinity = ^ disas/libvixl/a64/instructions-a64.h:107:21: error: 'vixl::kFP64SignallingNaN' defined but not used [-Werror=unused-variable] static const double kFP64SignallingNaN = ^ disas/libvixl/a64/instructions-a64.h:109:20: error: 'vixl::kFP32SignallingNaN' defined but not used [-Werror=unused-variable] static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001); ^ disas/libvixl/a64/instructions-a64.h:112:21: error: 'vixl::kFP64QuietNaN' defined but not used [-Werror=unused-variable] static const double kFP64QuietNaN = ^ disas/libvixl/a64/instructions-a64.h:114:20: error: 'vixl::kFP32QuietNaN' defined but not used [-Werror=unused-variable] static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001); ^ disas/libvixl/a64/instructions-a64.h:117:21: error: 'vixl::kFP64DefaultNaN' defined but not used [-Werror=unused-variable] static const double kFP64DefaultNaN = ^ disas/libvixl/a64/instructions-a64.h:119:20: error: 'vixl::kFP32DefaultNaN' defined but not used [-Werror=unused-variable] static const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000); ^ cc1plus: all warnings being treated as errors make: *** [disas/arm-a64.o] Error 1 Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> [PMM: Rewrote the commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24arm_gic: remove unused parameter.KONRAD Frederic
This removes num_irq parameter from gic_init_irqs_and_distributor as it is not used. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1412859651-15060-1-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24disas/libvixl: Update to libvixl 1.6Peter Maydell
Update our copy of libvixl to upstream 1.6. There are no changes of any particular interest to QEMU, so this is simply keeping up with current upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412091418-25744-1-git-send-email-peter.maydell@linaro.org
2014-10-24hw/arm/boot: register cpu reset handlers if using -biosArd Biesheuvel
Move the registering of CPU reset handlers to before the point where we leave the function in the -bios (not -kernel) case, so CPU reset works correctly with -bios as well. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24hw/arm/virt: mark timer in fdt as v8-compatibleClaudio Fontana
check if the first cpu is an armv8 cpu, and if so, put arm,armv8-timer in the compatible string list. Note that due to this check, this patch moves the creation of the timer fdt node to after the cpu creation loop. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Message-id: 1411736960-24206-1-git-send-email-hw.claudio@gmail.com [PMM: updated to list arm,armv8-timer first] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24hmp: Remove "info pcmcia"Markus Armbruster
This command lists PCMCIA sockets and cards. Only a few ARM boards have sockets (akita, borzoi, connex, mainstone, spitz, terrier, tosa, verdex, z2), the only card is the DSCM-1xxxx Hitachi Microdrive (qdev "microdrive"), and it is only inserted during machine init, if ever. So this command doesn't really tell anybody anything new so far. Moreover, pcmcia_socket_unregister() has a use-after-free bug, flagged by Coverity. Has never been used, because there has never been code to eject a PCMCIA card. Not worth fixing & converting to QMP. Remove it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Acked-by: Andreas Färber <afaerber@suse.de> Message-id: 1411144812-22958-1-git-send-email-armbru@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block patches # gpg: Signature made Thu 23 Oct 2014 18:56:05 BST using RSA key ID C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" * remotes/kevin/tags/for-upstream: (32 commits) qemu-img: Print error if check failed block: char devices on FreeBSD are not behind a pager iotests: Add test for qcow2 L1 table update qcow2: Do not overflow when writing an L1 sector iotests: Add test for map commands qemu-io: Respect early image end for map block: Respect underlying file's EOF docs/qcow2: Limit refcount_order to [0, 6] docs/qcow2: Correct refcount_block_entries qcow2: Drop REFCOUNT_SHIFT iotests: Add test for potentially damaging repairs iotests: Fix test outputs qcow2: Clean up after refcount rebuild qcow2: Rebuild refcount structure during check qcow2: Do not perform potentially damaging repairs qcow2: Fix refcount blocks beyond image end qcow2: Reuse refcount table in calculate_refcounts() qcow2: Let inc_refcounts() resize the reftable qcow2: Let inc_refcounts() return -errno qcow2: Split fail code in L1 and L2 checks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-23Merge remote-tracking branch 'mreitz/block' into queue-blockKevin Wolf
* mreitz/block: qemu-img: Print error if check failed block: char devices on FreeBSD are not behind a pager
2014-10-23qemu-img: Print error if check failedMax Reitz
Currently, if bdrv_check() fails either by returning -errno or having check_errors set, qemu-img check just exits with 1 after having told the user that there were no errors on the image. This is bad. Instead of printing the check result if there were internal errors which were so bad that bdrv_check() could not even complete with 0 as a return value, qemu-img check should inform the user about the error. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-10-23Merge remote-tracking branch 'remotes/qmp-unstable/tags/for-upstream' into ↵Peter Maydell
staging QMP patches # gpg: Signature made Thu 23 Oct 2014 16:05:52 BST using RSA key ID E24ED5A7 # gpg: Good signature from "Luiz Capitulino <lcapitulino@gmail.com>" * remotes/qmp-unstable/tags/for-upstream: monitor: delete device_del_bus_completion monitor: add del completion for peripheral device qdev: add qdev_build_hotpluggable_device_list helper MAINTAINERS: add entry for qobject files dump: Turn some functions to void to make code cleaner dump: Propagate errors into qmp_dump_guest_memory() virtio-balloon: Tweak recent fix for integer overflow Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-23block: char devices on FreeBSD are not behind a pagerRoger Pau Monne
Introduce a new flag to mark devices that require requests to be aligned and replace the usage of BDRV_O_NOCACHE and O_DIRECT with this flag when appropriate. If a character device is used as a backend on a FreeBSD host set this flag unconditionally. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2014-10-23get_maintainer.pl: restrict cases where it falls back to --gitPaolo Bonzini
The list emitted by --git-fallback often leads inexperienced contributors to add pointless CCs. While not discouraging usage of --git-fallback, we want to: 1) disable the fallback if only some files lack a maintainer $ scripts/get_maintainer.pl -f util/cutils.c hw/ide/core.c Kevin Wolf <kwolf@redhat.com> (odd fixer:IDE) Stefan Hajnoczi <stefanha@redhat.com> (odd fixer:IDE) This behavior is taken even if --git-fallback is specified. 2) warn the contributors about what we're doing, asking them to use their common sense: $ scripts/get_maintainer.pl -f util/cutils.c get_maintainer.pl: No maintainers found, printing recent contributors. get_maintainer.pl: Do not blindly cc: them on patches! Use common sense. Luiz Capitulino <lcapitulino@redhat.com> (commit_signer:1/2=50%) ... $ Explicitly disabling the fallback will not result in the warning message: $ scripts/get_maintainer.pl -f util/cutils.c --no-git-fallback $ echo $? 0 (Returning 1 would break usage of scripts/get_maintainer.pl as a cccmd for git-send-email). Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23get_maintainer.pl: move git loop under "if ($email) {"Paolo Bonzini
All checks in the loop are guarded by that condition, and there is a handy "if" just below. Simplify the code. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qtest: fix qtest log fd should be initialized before qtest chardevLi Liu
qtest_log_fp should be inited before qemu_chr_add_handlers. If not the log dumped from callback functions may be lost. easy to reproduce it by command: "QTEST_LOG=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 gtester -k --verbose -m=quick tests/qdev-monitor-test" The log "[I xxxxxx] OPENED" should be printed out by qtest_event, but does not. Signed-off-by: Li Liu <john.liuli@huawei.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: avoid M entries that point to mailing listsPaolo Bonzini
"L" entries that point to qemu-devel are not much better either, but at least the get_maintainer.pl output is clearer. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: add some tests directoriesPaolo Bonzini
Low-hanging fruit... Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: Add more TCG filesPaolo Bonzini
Unfortunately, TCG files do not really have a maintainer yet. But at least there will be fewer unmaintained files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: add myself for X86Paolo Bonzini
Still not moving it beyond "Odd fixes". Richard Henderson also has reviewed a bunch of X86 TCG patches, so add him as well. All we want is to avoid that patches fall on the floor. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: add Samuel Thibault as usb-serial.c and baum.c maintainerPaolo Bonzini
He wrote "I've written mostly all of usb-serial.c and baum.c, and keep maintaining them, since I use them regularly." Cc: Samuel Thibault <samuel.thibault@ens-lyon.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23MAINTAINERS: grab more files from Anthony's pilePaolo Bonzini
I am picking up character devices and the main loop, as agreed during QEMU Summit. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23target-i386: warns users when CPU threads>1 for non-Intel CPUsWei Huang
Only Intel CPUs support hyperthreading. When users select threads>1 in -smp option, QEMU fixes it by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX based on inputs (sockets, cores, threads); so guest VM can boot correctly. However it is still better to gives users a warning when such case happens. Signed-off-by: Wei Huang <wei@redhat.com> [As suggested by Eduardo, check for !IS_INTEL instead of AMD. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23sysbus: Use TYPE_DEVICE GPIO functionalityPeter Crosthwaite
Re-implement the Sysbus GPIOs to use the existing TYPE_DEVICE GPIO named framework. A constant string name is chosen to avoid conflicts with existing unnamed GPIOs. This unifies GPIOs are IRQs for sysbus devices and allows removal of all Sysbus state for GPIOs. Any existing and future-added functionality for GPIOs is now also available for sysbus IRQs. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qdev: gpio: Define qdev_pass_gpios()Peter Crosthwaite
Allows a container to take ownership of GPIOs in a contained device and automatically connect them as GPIOs to the container. This prepares for deprecation of the SYSBUS IRQ functionality, which has this feature. We push it up to the device level instead of sysbus level. There's nothing sysbus specific about passing GPIOs to containers so its a legitimate device-level generic feature. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qdev: gpio: Remove qdev_init_gpio_out x1 restrictionPeter Crosthwaite
Previously this was restricted to a single call per-dev/per-name. With the conversion of the GPIO output state to QOM the implementation can now handle repeated calls. Remove the restriction. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qdev: gpio: delete NamedGPIOList::outPeter Crosthwaite
All users of GPIO outputs are fully QOMified, using QOM properties to access the GPIO data. Delete. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23irq: Remove qemu_irq_intercept_outPeter Crosthwaite
No more users left and obsoleted by qdev_intercept_gpio_out. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qtest/irq: Rework IRQ interceptionPeter Crosthwaite
Change the qtest intercept handler to accept just the individual IRQ being intercepted as opaque. n is still expected to be correctly set as for the original intercepted irq. qemu_intercept_irq_in is updated accordingly. Then covert the qemu_irq_intercept_out call to use qdev intercept version. This stops qtest from having to mess with the raw IRQ pointers (still has to mess with names and counts but a step in the right direction). Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qdev: gpio: Add API for intercepting a GPIOPeter Crosthwaite
To replace the old qemu_irq intercept API (which had users reaching into qdev private state for GPIOs). Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qdev: gpio: Re-implement qdev_connect_gpio QOM stylePeter Crosthwaite
Re-implement as a link setter. This should allow the QOM framework to keep track of ref counts properly etc. We need to add a default parent for the connecting input incase it's coming from a non-qdev source. We simply parent the IRQ to the machine in this case. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-10-23qom: Demote already-has-a-parent to a regular errorPeter Crosthwaite
Rather than an abort(). This allows callers to decide whether parenting an already-parented object is a fatal error condition. Useful for providing a default value for an object's parent in the case where you want to set one iff it doesn't already have one. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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