aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-03-08s390/ipl: only print boot menu error if -boot menu=on was specifiedCollin L. Walling
It is possible that certain QEMU configurations may not create an IPLB (such as when -kernel is provided). In this case, a misleading error message will be printed stating that the "boot menu is not supported for this device type". To amend this, only print this message iff boot menu=on was provided on the commandline. Otherwise, return silently. While we're at it, remove trailing periods from error messages. Signed-off-by: Collin L. Walling <walling@linux.vnet.ibm.com> Message-Id: <1519760121-24594-1-git-send-email-walling@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08hw/s390x/ipl: Bail out if the network bootloader can not be foundThomas Huth
If QEMU fails to load 's390-netboot.img', the guest firmware currently loops forever and just floods the console with "Network boot device detected" messages. The code in ipl.c apparently already tried to stop the VM with vm_stop() in this case, but this is in vain since the run state is later reset due to a call to vm_start() from vl.c again. To avoid the ugly firmware loop, let's simply exit QEMU directly instead since it just does not make sense to continue if the required firmware image can not be loaded. While we're at it, also add the file name of the netboot binary to the error message, so that the user has a better hint about what is missing. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519725913-24852-1-git-send-email-thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Farhan Ali <alifm@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-08.shippable.yml: disable powerpc-cross imageAlex Bennée
Something has happened to the old emdebian setup which means it no longer builds. Let's disable the shippable builds which are always failing. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-03-08Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell
staging qemu-sparc update # gpg: Signature made Thu 08 Mar 2018 07:23:01 GMT # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sparc: fix leon3 casa instruction when MMU is disabled hw/sparc/sun4m: Fix implicit creation of "-drive if=scsi" devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08Merge remote-tracking branch ↵Peter Maydell
'remotes/stefanberger/tags/pull-tpm-2018-03-07-1' into staging Merge tpm 2018/03/07 # gpg: Signature made Wed 07 Mar 2018 12:42:13 GMT # gpg: using RSA key 75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2018-03-07-1: tpm: convert tpm_tis.c to use trace-events tpm: convert tpm_emulator.c to use trace-events tpm: convert tpm_util.c to use trace-events tpm: convert tpm_passthrough.c to use trace-events tpm: convert tpm_crb.c to use trace-events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08Merge remote-tracking branch 'remotes/berrange/tags/qio-next-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Wed 07 Mar 2018 11:24:41 GMT # gpg: using RSA key BE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/qio-next-pull-request: qio: non-default context for TLS handshake qio: non-default context for async conn qio: non-default context for threaded qtask qio: store gsources for net listeners qio: introduce qio_channel_add_watch_{full|source} qio: rename qio_task_thread_result Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Multiboot patches # gpg: Signature made Wed 07 Mar 2018 11:15:17 GMT # gpg: using RSA key 7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: multiboot: fprintf(stderr...) -> error_report() multiboot: Use header names when displaying fields multiboot: Remove unused variables from multiboot.c multiboot: bss_end_addr can be zero Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-08sparc: fix leon3 casa instruction when MMU is disabledKONRAD Frederic
Since the commit af7a06bac7d3abb2da48ef3277d2a415772d2ae8: `casa [..](10), .., ..` (and probably others alternate space instructions) triggers a data access exception when the MMU is disabled. When we enter get_asi(...) dc->mem_idx is set to MMU_PHYS_IDX when the MMU is disabled. Just keep mem_idx unchanged in this case so we passthrough the MMU when it is disabled. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-03-08hw/sparc/sun4m: Fix implicit creation of "-drive if=scsi" devicesThomas Huth
The global hack for creating SCSI devices has recently been removed, but this apparently broke SCSI devices on some boards that were not ready for this change yet. For the sun4m machines you now get: $ sparc-softmmu/qemu-system-sparc -boot d -cdrom x.iso qemu-system-sparc: -cdrom x.iso: machine type does not support if=scsi,bus=0,unit=2 Fix it by calling scsi_bus_legacy_handle_cmdline() after creating the corresponding SCSI controller. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: 1454509726719e0933c800fad00d6999752688ea Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-03-07multiboot: fprintf(stderr...) -> error_report()Jack Schwartz
Change all fprintf(stderr...) calls in hw/i386/multiboot.c to call error_report() instead, including the mb_debug macro. Remove the "\n" from strings passed to all modified calls, since error_report() appends one. Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: Use header names when displaying fieldsJack Schwartz
Refer to field names when displaying fields in printf and debug statements. Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: Remove unused variables from multiboot.cJack Schwartz
Remove unused variables: mh_mode_type, mh_width, mh_height, mh_depth Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07multiboot: bss_end_addr can be zeroJack Schwartz
The multiboot spec (https://www.gnu.org/software/grub/manual/multiboot/), section 3.1.3, allows for bss_end_addr to be zero. A zero bss_end_addr signifies there is no .bss section. Suggested-by: Daniel Kiper <daniel.kiper@oracle.com> Signed-off-by: Jack Schwartz <jack.schwartz@oracle.com> Reviewed-by: Daniel Kiper <daniel.kiper@oracle.com> Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2018-03-07RISC-V Build InfrastructureMichael Clark
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark
This provides a RISC-V Board compatible with the the SiFive Freedom U SDK. The following machine is implemented: - 'sifive_u'; CLINT, PLIC, UART, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark
This provides a RISC-V Board compatible with the the SiFive Freedom E SDK. The following machine is implemented: - 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PRCI BlockMichael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V UART DeviceMichael Clark
QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V VirtIO MachineMichael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V Test FinisherMichael Clark
Test finisher memory mapped device used to exit simulation. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V Spike MachinesMichael Clark
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V PLIC BlockMichael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07SiFive RISC-V CLINT BlockMichael Clark
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HART ArrayMichael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V HTIF ConsoleMichael Clark
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Stefan O'Rear <sorear2@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07Add symbol table callback interface to load_elfMichael Clark
The RISC-V HTIF (Host Target Interface) console device requires access to the symbol table to locate the 'tohost' and 'fromhost' symbols. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V Linux User EmulationMichael Clark
Implementation of linux user emulation for RISC-V. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V Physical Memory ProtectionMichael Clark
Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daire McNamara <daire.mcnamara@emdalo.com> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V TCG Code GenerationMichael Clark
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V GDB StubMichael Clark
GDB Register read and write routines. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V FPU SupportMichael Clark
Helper routines for FPU instructions and NaN definitions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V CPU HelpersMichael Clark
Privileged control and status register helpers and page fault handling. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V DisassemblerMichael Clark
The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V CPU Core DefinitionMichael Clark
Add CPU state header, CPU definitions and initialization routines Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V ELF Machine DefinitionMichael Clark
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07RISC-V MaintainersMichael Clark
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-06tpm: convert tpm_tis.c to use trace-eventsStefan Berger
Leave the DEBUG_TIS for more debugging and convert to use if (DEBUG_TIS) rather than #if DEBUG_TIS where it is being used. Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_emulator.c to use trace-eventsStefan Berger
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_util.c to use trace-eventsStefan Berger
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_passthrough.c to use trace-eventsStefan Berger
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06tpm: convert tpm_crb.c to use trace-eventsStefan Berger
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2018-03-06misc: don't use hwaddr as a type in trace eventsDaniel P. Berrangé
Use types that are defined by QEMU in trace events caused build failures for the UST trace backend: In file included from trace-ust-all.c:13:0: trace-ust-all.h:11844:206: error: unknown type name ‘hwaddr’ It only knows about C built-in types, and any types that are pulled in from includs of qemu-common.h and lttng/tracepoint.h. This does not include the 'hwaddr' type, so replace it with a uint64_t which is what exec/hwaddr.h defines 'hwaddr' as. This fixes the build failure introduced by commit 9eb8040c2d2b38e1a40bb6129b1b668fa178fcab Author: Peter Maydell <peter.maydell@linaro.org> Date: Fri Mar 2 10:45:39 2018 +0000 hw/misc/tz-ppc: Model TrustZone peripheral protection controller Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180306134317.836-1-berrange@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* new QMP command qom-list-properties (Alexey) * TCG cleanups (David) * use g_path_get_basename/g_path_get_dirname when useful (Julia) * WHPX fixes (Justin) * ASAN fixes (Marc-André) * g364fb memory leak fix, address_space_to_flatview RCU fixes (me) * chardev memory leak fix (Peter) * checkpatch improvements (Julia, Su Hang) * next round of deprecation patches (Thomas) # gpg: Signature made Tue 06 Mar 2018 13:11:58 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (34 commits) use g_path_get_basename instead of basename balloon: Fix documentation of the --balloon parameter and deprecate it WHPX improve interrupt notification registration WHXP Removes the use of WHvGetExitContextSize Fix WHPX issue leaking tpr values Fix WHPX typo in 'mmio' Fix WHPX additional lock acquisition Remove unnecessary WHPX __debugbreak(); Resolves WHPX breaking changes in SDK 17095 Fixing WHPX casing to match SDK Revert "build-sys: compile with -Og or -O1 when --enable-debug" checkpatch: add check for `while` and `for` checkpatch: add a warning for basename/dirname address_space_rw: address_space_to_flatview needs RCU lock address_space_map: address_space_to_flatview needs RCU lock address_space_access_valid: address_space_to_flatview needs RCU lock address_space_read: address_space_to_flatview needs RCU lock address_space_write: address_space_to_flatview needs RCU lock memory: inline some performance-sensitive accessors openpic_kvm: drop address_space_to_flatview call ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-06use g_path_get_basename instead of basenameJulia Suvorova
basename(3) and dirname(3) modify their argument and may return pointers to statically allocated memory which may be overwritten by subsequent calls. g_path_get_basename and g_path_get_dirname have no such issues, and therefore more preferable. Signed-off-by: Julia Suvorova <jusual@mail.ru> Message-Id: <1519888086-4207-1-git-send-email-jusual@mail.ru> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06balloon: Fix documentation of the --balloon parameter and deprecate itThomas Huth
There are two issues with the documentation of the --balloon parameter: First, "--balloon none" is simply doing nothing. Even if a machine had a balloon device by default, this option is not disabling anything, it is simply ignored. Thus let's simply drop this option from the documentation to avoid to confuse the users (but keep the code in vl.c for backward compatibility). Second, the documentation claims that "--balloon virtio" is the default mode, but this is not true anymore since commit 382f074371f7dc32a34. Since that commit, the option also has no real use case anymore, since you can simply use "--device virtio-balloon" nowadays instead. Thus to simplify our complex parameter zoo a little bit, let's deprecate the the parameter now and tell the user to use "--device virtio-balloon" instead. Fixes: 382f074371f7dc32a34c944c845b1698e83d8c36 Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1519796303-13257-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-06WHPX improve interrupt notification registrationJustin Terry (VM) via Qemu-devel
Improves the usage of the InterruptNotification registration by skipping the additional call to WHvSetVirtualProcessorRegisters if we have already registered for the window exit. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1519665216-1078-9-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
2018-03-06WHXP Removes the use of WHvGetExitContextSizeJustin Terry (VM) via Qemu-devel
The use of WHvGetExitContextSize will break ABI compatibility if the platform changes the context size while a qemu compiled executable does not recompile. To avoid this we now use sizeof and let the platform determine which version of the struction was passed for ABI compatibility. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1519665216-1078-8-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
2018-03-06Fix WHPX issue leaking tpr valuesJustin Terry (VM) via Qemu-devel
Fixes an issue where if the tpr is assigned to the array but not a different value from what is already expected on the vp the code will skip incrementing the reg_count. In this case its possible that we set an invalid memory section of the next call for DeliverabilityNotifications that was not expected. The fix is to use a local variable to store the temporary tpr and only update the array if the local tpr value is different than the vp context. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1519665216-1078-7-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
2018-03-06Fix WHPX typo in 'mmio'Justin Terry (VM) via Qemu-devel
Renames the usage of 'memio' to 'mmio' in the emulator callbacks. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1519665216-1078-6-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
2018-03-06Fix WHPX additional lock acquisitionJustin Terry (VM) via Qemu-devel
The code already is holding the qemu_mutex for the IO thread. We do not need to additionally take the lock again in this case. Signed-off-by: Justin Terry (VM) <juterry@microsoft.com> Message-Id: <1519665216-1078-5-git-send-email-juterry@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 18:52:15 +0000