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2013-04-29pc: QOM'ify port 92Andreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-12-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29parallel: QOM'ifyAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-11-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29ne2000-isa: QOM'ifyAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-10-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29mc146818rtc: QOM'ifyAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-9-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29m48t59: QOM'ify ISA M48T59 NVRAMAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST() and container_of(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-8-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29ide: QOM'ify ISA IDEAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Add missing braces. Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-7-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29i8259: QOM cleanupsAndreas Färber
Eliminate DO_UPCAST() for PICCommonState. Prepares for ISA realizefn. Also give the i8259_common type registration functions unique names while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-6-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29i82374: QOM'ifyAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-5-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29fdc: QOM'ify ISA floppy controllerAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Reuse type constant for PC machine compatibility settings. Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-4-git-send-email-afaerber@suse.de Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29cirrus_vga: QOM'ify ISA Cirrus VGAAndreas Färber
Introduce type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-3-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29applesmc: QOM'ifyAndreas Färber
Add a typedef for the state struct and rename from Status to State. Add type constant and cast macro to obsolete DO_UPCAST(). Prepares for ISA realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-2-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29virtio-net: unbreak the minix guestJason Wang
Multiqueue patchset conditionally add control vq only when guest negotiate the feature. Though the spec is not clear on this but it breaks the minix guest since it will identify the ctrl vq even if it does not support it. Though this behavior seems a violation on the spec "If the VIRTIO_NET_F_CTRL_VQ feature bit is negotiated, identify the control virtqueue.", to keep the backward compatibility, always add the ctrl vq at end of the queues. Reported-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-id: 1366874663-2566-1-git-send-email-jasowang@redhat.com Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29Merge remote-tracking branch 'bonzini/migration-writev' into stagingAnthony Liguori
# By Paolo Bonzini # Via Paolo Bonzini * bonzini/migration-writev: win32: add readv/writev emulation win32: generate console executable again win32: move Makefile dependencies on version-obj-y to rules.mak win32: add generic RC rules to rules.mak Message-id: 1367230284-24612-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29Merge remote-tracking branch 'alon/libcacard_ccid.2' into stagingAnthony Liguori
# By Cole Robinson # Via Alon Levy * alon/libcacard_ccid.2: ccid: Fix crash when backend isn't specified Message-id: 20130426234357.GA12457@garlic.tami Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-29win32: add readv/writev emulationPaolo Bonzini
Commit e9d8fbf (qemu-file: do not use stdio for qemu_fdopen, 2013-03-27) introduced a usage of writev, which mingw32 does not have. Even though qemu_fdopen itself is not used on mingw32, the future-proof solution is to add an implementation of it. This is simple and similar to how we emulate sendmsg/recvmsg in util/iov.c. Some files include osdep.h without qemu-common.h, so move the definition of iovec to osdep.h too, and include osdep.h from qemu-common.h unconditionally (protection against including files when NEED_CPU_H is defined is not needed since the removal of AREG0). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-27sparc64: use direct interrupt mapping for PCI devicesArtyom Tarasenko
Every PCI Slot in PBM has 4 directly mapped IRQ lines. Use the IRQ routing schema 0bssnn (Bus, Slot, interrupt Number) described in Section 19.3.3 of UltraSPARC™-IIi User's Manual. Please note that this patch requires the OpenBIOS counterpart patch. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: fix loosing interruptsArtyom Tarasenko
- clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: allow 64 IRQ linesArtyom Tarasenko
According to UltraSPARC™-IIi User’s Manual, PBM has 64 IRQ lines. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27tcg-arm: Remove long jump from tcg_out_goto_labelRichard Henderson
Branches within a TB will always be within 16MB. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson
Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use movi32 + blx for calls on v7Richard Henderson
Work better with branch predition when we have movw+movt, as the size of the code is the same. Perhaps re-evaluate when we have a proper constant pool. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Delete the 'S' constraintRichard Henderson
After the previous patch, 's' and 'S' are the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve scheduling of tcg_out_tlb_readRichard Henderson
The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Split out tcg_out_tlb_readRichard Henderson
Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup most primitive load store subroutinesRichard Henderson
Use even more primitive helper functions to avoid lots of duplicated code. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup multiply subroutinesRichard Henderson
Make the code more readable by only having one copy of the magic numbers, swapping registers as needed prior to that. Speed the compiler by not applying the rd == rn avoidance for v6 or later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use R12 for the tcg temporaryRichard Henderson
R12 is call clobbered, while R8 is call saved. This change gives tcg one more call saved register for real data. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use TCG_REG_TMP name for the tcg temporaryRichard Henderson
Don't hard-code R8. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement division instructionsRichard Henderson
An armv7 extension implements division, present on Cortex A15. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement deposit for armv7Richard Henderson
We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve constant generationRichard Henderson
Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Handle constant arguments to add2/sub2Richard Henderson
We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use tcg_out_dat_rIN for comparesRichard Henderson
This allows us to emit CMN instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Allow constant first argument to subRichard Henderson
This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Handle negated constant arguments to and/subRichard Henderson
This greatly improves code generation for addition of small negative constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use bic to implement and with constantRichard Henderson
This greatly improves the code we can produce for deposit without armv7 support. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg: Log the contents of the prologue with -d out_asmRichard Henderson
This makes it easier to verify changes to the code generating the prologue. [Aurelien: change the format from %i to %zu] Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27ccid: Fix crash when backend isn't specifiedCole Robinson
Reproducer: ./x86_64-softmmu/qemu-system-x86_64 -device usb-ccid,id=ccid0 -usb -device ccid-card-emulated -monitor stdio Signed-off-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Alon Levy <alevy@redhat.com>
2013-04-27tcg-arm: Fix local stack frameRichard Henderson
We were not allocating TCG_STATIC_CALL_ARGS_SIZE, so this meant that any helper with more than 4 arguments would clobber the saved regs. Realizing that we're supposed to have this memory pre-allocated means we can clean up the tcg_out_arg functions, which were trying to do more stack allocation. Allocate stack memory for the TCG temporaries while we're at it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg: fix deposit_i64 op on 32-bit targetsAurelien Jarno
On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 + deposit_i32, care should be taken to not overwrite the low part of the second argument before the deposit when it is the same the destination. This fixes the shld instruction in qemu-system-x86_64, which in turns fixes booting "system rescue CD version 2.8.0" on this target. Reported-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-27target-ppc: slightly optimize lfiwaxAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-27Merge branch 'ppc-for-upstream' of git://github.com/agraf/qemuAurelien Jarno
* 'ppc-for-upstream' of git://github.com/agraf/qemu: (30 commits) target-ppc: add support for extended mtfsf/mtfsfi forms target-ppc: emulate store doubleword pair instructions target-ppc: emulate load doubleword pair instructions target-ppc: emulate lfiwax instruction target-ppc: emulate fcpsgn instruction target-ppc: emulate prtyw and prtyd instructions target-ppc: emulate cmpb instruction target-ppc: add instruction flags for Book I 2.05 disas: Disassemble all ppc insns for the guest target-ppc: optimize fabs, fnabs, fneg PPC: Fix dcbz for linux-user on 970 powerpc: correctly handle fpu exceptions. pseries: Generate device paths for VIO devices pseries: Convert VIO code to QOM style type safe(ish) casts target-ppc: Synchronize VPA state with KVM pseries: Fix some small errors in XICS logic target-ppc: Add more stubs for POWER7 PMU registers pseries: Fixes and enhancements to L1 cache properties pseries: Fix incorrect calculation of RMA size in certain configurations PPC: Fix compile with profiling enabled ...
2013-04-27win32: generate console executable againPaolo Bonzini
The -mwindows option is not anymore in LIBS at this point of the Makefile, it is only in libs_softmmu. Check the right variable. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-27win32: move Makefile dependencies on version-obj-y to rules.makPaolo Bonzini
This makes the test on $(LIBTOOL) work. Otherwise, LIBTOOL is /bin/false by the time the test is done. Fixes Win32 compilation without a working cross-libtool. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-27win32: add generic RC rules to rules.makPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-26target-ppc: add support for extended mtfsf/mtfsfi formsAurelien Jarno
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new W field to select the upper part of the FPCSR register. For that the helper is changed to handle 64-bit input values and mask with up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit marked as invalid anymore. Instead this is checked in the helper, which therefore needs to access to the insns/insns_flags2. They are added in the DisasContext struct. Finally change all accesses to the opcode fields through extract helpers, prefixed with FP for consistency. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate store doubleword pair instructionsAurelien Jarno
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate load doubleword pair instructionsAurelien Jarno
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate lfiwax instructionAurelien Jarno
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: fix tcg debug error] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-26target-ppc: emulate fcpsgn instructionAurelien Jarno
Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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