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2022-01-07bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.hWarner Losh
2022-01-07bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontextWarner Losh
2022-01-07bsd-user/i386: Move the inlines into signal.cWarner Losh
2022-01-07bsd-user/i386/target_arch_signal.h: Update mcontext_t to match FreeBSDWarner Losh
2022-01-07bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.hWarner Losh
2022-01-07bsd-user/i386/target_arch_signal.h: Remove target_sigcontextWarner Losh
2022-01-07bsd-user: create a per-arch signal.c fileWarner Losh
2022-01-07bsd-user/freebsd: Create common target_os_ucontext.h fileWarner Losh
2022-01-07bsd-user/mips*: Remove mips supportWarner Losh
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot
2022-01-08qemu/int128: addition of div/rem 128-bit operationsFrédéric Pétrot
2022-01-08exec/memop: Adding signed quad and octo definesFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08roms/opensbi: Upgrade from v0.9 to v1.0Bin Meng
2022-01-08hw/riscv: virt: Allow support for 32 coresAlistair Francis
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis
2022-01-08hw/intc: sifive_plic: Cleanup remaining functionsAlistair Francis
2022-01-08hw/intc: sifive_plic: Cleanup the read functionAlistair Francis
2022-01-08hw/intc: sifive_plic: Cleanup the write functionAlistair Francis
2022-01-08hw/intc: sifive_plic: Add a reset functionAlistair Francis
2022-01-08hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registersJim Shu
2022-01-08hw/dma: sifive_pdma: support high 32-bit access of 64-bit registerJim Shu
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
2022-01-07Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu in...Richard Henderson
2022-01-07tests: acpi: Add updated TPM related tablesStefan Berger
2022-01-07acpi: tpm: Add missing device identification objectsStefan Berger
2022-01-07tests: acpi: prepare for updated TPM related tablesStefan Berger