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2017-07-19crypto: cipher: introduce context free functionLongpeng(Mike)
Refactors the qcrypto_cipher_free(), splits it into two parts. One is gcrypt/nettle__cipher_free_ctx() to free the special context. This makes code more clear, what's more, it would be used by the later patch. Reviewed-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2017-07-19Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-07-18-1' ↵Peter Maydell
into staging Merge I/O 2017/07/18 v1 # gpg: Signature made Tue 18 Jul 2017 11:31:53 BST # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qio-2017-07-18-1: io: simplify qio_channel_attach_aio_context Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18target/alpha: Log temp leaksRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_fbcondRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_call_palRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_mtprRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Fix temp leak in gen_bcondRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Merge several flag bytes into ENV->FLAGSRichard Henderson
The flags are arranged such that we can manipulate them either a whole, or as individual bytes. The computation within cpu_get_tb_cpu_state is now reduced to a single load and mask. Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Copy tb->flags into DisasContextRichard Henderson
Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/alpha: Remove amask from tb->flagsRichard Henderson
This value is constant for the cpu and does not need to be stored within the TB. Tested-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18target/sh4: Use tcg_gen_lookup_and_goto_ptrRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-28-rth@twiddle.net> [aurel32: fix whitespace] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Implement fsrraRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-27-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Add missing FPSCR.PR == 0 checksRichard Henderson
Both frchg and fschg require PR == 0, otherwise undefined_operation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-26-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Implement fpchgRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-25-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Introduce CHECK_SH4ARichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-24-rth@twiddle.net> [aurel32: fix conflict] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Introduce CHECK_FPSCR_PR_*Richard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-23-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Tidy misc illegal insn checksRichard Henderson
Now that we have a do_illegal label, use goto in order to self-document the forcing of the exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-22-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify code for CHECK_FPU_ENABLEDRichard Henderson
We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-21-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify code for CHECK_PRIVILEGEDRichard Henderson
We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-20-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify code for CHECK_NOT_DELAY_SLOTRichard Henderson
We do not need to emit N copies of raising an exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-19-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Simplify 64-bit fp reg-reg moveRichard Henderson
We do not need to form full 64-bit quantities in order to perform the move. This reduces code expansion on 64-bit hosts. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-18-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Load/store Dr as 64-bit quantitiesRichard Henderson
This enforces proper alignment and makes the register update more natural. Note that there is a more serious bug fix for fmov {DX}Rn,@(R0,Rn) to use a store instead of a load. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-17-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Merge DREG into fpr64 routinesRichard Henderson
Also add a debugging assert that we did signal illegal opc for odd double-precision registers. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-16-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Eliminate unused XREG macroRichard Henderson
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-15-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Hoist fp register bank selectionRichard Henderson
Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-14-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Pass DisasContext to fpr64 routinesRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-13-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Unify cpu_fregs into FREGRichard Henderson
We were treating FREG as an index and REG as a TCGv. Making FREG return a TCGv is both less confusing and a step toward cleaner banking of cpu_fregs. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-12-rth@twiddle.net> [aurel32: fix whitespace issues] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Hoist register bank selectionRichard Henderson
Compute which register bank to use once at the start of translation. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-11-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18linux-user/sh4: Clean env->flags on signal boundariesRichard Henderson
If a signal is delivered during the execution of a delay slot, or a gUSA region, clear those bits from the environment so that the signal handler does not start in that same state. Cleaning the bits on signal return is paranoid good sense. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-10-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18linux-user/sh4: Notice gUSA regions during signal deliveryRichard Henderson
We translate gUSA regions atomically in a parallel context. But in a serial context a gUSA region may be interrupted. In that case, restart the region as the kernel would. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-9-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Recognize common gUSA sequencesRichard Henderson
For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-8-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Handle user-space atomicsRichard Henderson
For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. For QEMU, we cannot do this in quite the same way. Instead, we notice the normal start of such a sequence (mov #-x,r15), and start a new TB that can be executed under cpu_exec_step_atomic. Reported-by: Bruno Haible <bruno@clisp.org> LP: https://bugs.launchpad.net/bugs/1701971 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-7-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Adjust TB_FLAG_PENDING_MOVCARichard Henderson
Don't leave an unused bit after DELAY_SLOT_MASK. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-6-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Keep env->flags cleanRichard Henderson
If we mask off any out-of-band bits before we assign to the variable, then we don't need to clean it up when reading. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-5-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Introduce TB_FLAG_ENVFLAGS_MASKRichard Henderson
We'll be putting more things into this bitmask soon. Let's have a name that covers all possible uses. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-4-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: Consolidate end-of-TB testsRichard Henderson
We can fold 3 different tests within the decode loop into a more accurate computation of max_insns to start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-3-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: return result of fcmp using TCGAurelien Jarno
Since that the T bit of the SR register is mapped using a TGC global, it's better to return the value through TCG than writing it directly. It allows to declare the helpers with the flag TCG_CALL_NO_WG. Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: do not use a helper to implement fnegAurelien Jarno
There is no need to use a helper to flip one bit, just use a TCG xor instruction instead. Message-Id: <20170702202814.27793-5-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: fix FPSCR cause vs flag inversionAurelien Jarno
The floating-point status/control register contains cause and flag bits. The cause bits are set to 0 before executing the instruction, while the flag bits hold the status of the exception generated after the field was last cleared. Message-Id: <20170702202814.27793-4-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: fix FPU unorderered compareAurelien Jarno
In case of unordered compare, the fcmp instructions should either trigger and invalid exception (if enabled) or set T=0. The existing code left it unchanged. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-3-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18target/sh4: do not check for PR bit for fabs instructionAurelien Jarno
The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18xen: don't use xenstore to save/restore physmap anymoreIgor Druzhinin
If we have a system with xenforeignmemory_map2() implemented we don't need to save/restore physmap on suspend/restore anymore. In case we resume a VM without physmap - try to recreate the physmap during memory region restore phase and remap map cache entries accordingly. The old code is left for compatibility reasons. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18xen/mapcache: introduce xen_replace_cache_entry()Igor Druzhinin
This new call is trying to update a requested map cache entry according to the changes in the physmap. The call is searching for the entry, unmaps it and maps again at the same place using a new guest address. If the mapping is dummy this call will make it real. This function makes use of a new xenforeignmemory_map2() call with an extended interface that was recently introduced in libxenforeignmemory [1]. [1] https://www.mail-archive.com/xen-devel@lists.xen.org/msg113007.html Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18xen/mapcache: add an ability to create dummy mappingsIgor Druzhinin
Dummys are simple anonymous mappings that are placed instead of regular foreign mappings in certain situations when we need to postpone the actual mapping but still have to give a memory region to QEMU to play with. This is planned to be used for restore on Xen. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18xen: move physmap saving into a separate functionIgor Druzhinin
Non-functional change. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
2017-07-18xen-platform: separate unplugging of NVMe disksStefano Stabellini
Commit 090fa1c8 "add support for unplugging NVMe disks..." extended the existing disk unplug flag to cover NVMe disks as well as IDE and SCSI. The recent thread on the xen-devel mailing list [1] has highlighted that this is not desirable behaviour: PV frontends should be able to distinguish NVMe disks from other types of disk and should have separate control over whether they are unplugged. This patch defines a new bit in the unplug mask for this purpose (see Xen commit [2]) and also tidies up the definitions of, and improves the comments regarding, the previously exiting bits in the protocol. [1] https://lists.xen.org/archives/html/xen-devel/2017-03/msg02924.html [2] http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=1096aa02 Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18xen_pt_msi.c: Check for xen_host_pci_get_* failures in xen_pt_msix_init()Peter Maydell
Check the return status of the xen_host_pci_get_* functions we call in xen_pt_msix_init(), and fail device init if the reads failed rather than ploughing ahead. (Spotted by Coverity: CID 777338.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18hw/xen: Set emu_mask for igd_opregion registerXiong Zhang
In igd passthrough environment, guest could only access opregion at the first bootup time. Once guest shutdown, later guest couldn't access opregion anymore. This is because qemu set emulated guest opregion base address to host register. Later guest get a wrong host opregion base address, and couldn't access it anymore. This patch set emu_mask for igd_opregion register, so guest won't set guest opregion base address to host. Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170718' into ↵Peter Maydell
staging s390: add z14 cpu model - add a CPU model for the IBM z14 which was announced on July 17th 2017 - update linux headers to 4.13-rc0 to get a fix for an ioctl definition # gpg: Signature made Tue 18 Jul 2017 09:56:24 BST # gpg: using RSA key 0x117BBC80B5A61C7C # gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>" # Primary key fingerprint: F922 9381 A334 08F9 DBAB FBCA 117B BC80 B5A6 1C7C * remotes/borntraeger/tags/s390x-20170718: s390x/cpumodel: z14 cpu models linux header sync against v4.13-rc1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into stagingPeter Maydell
# gpg: Signature made Tue 18 Jul 2017 05:15:03 BST # gpg: using RSA key 0xBDBE7B27C0DE3057 # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>" # gpg: aka "Jeffrey Cody <jeff@codyprime.org>" # gpg: aka "Jeffrey Cody <codyprime@gmail.com>" # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98 D624 BDBE 7B27 C0DE 3057 * remotes/cody/tags/block-pull-request: live-block-ops.txt: Rename, rewrite, and improve it bitmaps.md: Convert to rST; move it into 'interop' dir Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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