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2018-08-20s390x: Enable KVM huge page backing supportJanosch Frank
QEMU has had huge page support for a longer time already, but KVM memory management under s390x needed some changes to work with huge backings. Now that we have support, let's enable it if requested and available. Otherwise we now properly tell the user if there is no support and back out instead of failing to run the VM later on. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20180802070201.257406-1-frankja@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x/kvm: add etoken facilityChristian Borntraeger
Provide the etoken facility. We need to handle cpu model, migration and clear reset. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Janosch Frank <frankja@linux.ibm.com> Message-Id: <20180731090448.36662-3-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20linux-headers: updateCornelia Huck
Update to Linux upstream commit 2ad0d5269970 ("Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net") Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x/cpumodel: Add "-cpu max" supportDavid Hildenbrand
The "max" CPU model behaves like "-cpu host" when KVM is enabled, and like a CPU with the maximum possible feature set when TCG is enabled. While the "host" model can not be used under TCG ("kvm_required"), the "max" model can and "Enables all features supported by the accelerator in the current host". So we can treat "host" just as a special case of "max" (like x86 does). It differs to the "qemu" CPU model under TCG such that compatibility handling will not be performed and that some experimental CPU features not yet part of the "qemu" model might be indicated. These are right now under TCG (see "qemu_MAX"): - stfle53 - msa5-base - zpci This will result right now in the following warning when starting QEMU TCG with the "max" model: "qemu-system-s390x: warning: 'msa5-base' requires 'kimd-sha-512'." The "qemu" model (used as default in QEMU under TCG) will continue to work without such warnings. The "max" model in the current form might be interesting for kvm-unit-tests (where we would e.g. now also test "msa5-base"). The "max" model is neither static nor migration safe (like the "host" model). It is independent of the machine but dependends on the accelerator. It can be used to detect the maximum CPU model also under TCG from upper layers without having to care about CPU model names for CPU model expansion. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180725091233.3300-1-david@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [CH: minor wording changes] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x: remove 's390-squash-mcss' optionCornelia Huck
This option has been deprecated for two releases; remove it. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x/cpumodel: enum type S390FeatGroup now gets generatedMichael Mueller
The enumeration type S390FeatGroup is now generated as well. This shall simplify the definition of new feature groups without the requirement to modify existing code. Signed-off-by: Michael Mueller <mimu@linux.ibm.com> Message-Id: <20180725143617.8731-1-mimu@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x: introduce 3.1 compat machineCornelia Huck
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20tests/boot-serial-test: Bump timeout to 6 minutesPeter Maydell
On a SPARC host that I'm using as a build test machine, the boot-serial-test for the SPARC guest machines takes about 65 seconds to execute. This means that it hits the current 60 second timer on these tests. Push the timeout up so that it doesn't trigger spuriously on slow hosts like this one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20180817161404.9420-1-peter.maydell@linaro.org
2018-08-20Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2018-08-17 * Allow machine classes to specify if boot device suffixes should be ignored by get_boot_devices_list() * Tiny coding style fixup # gpg: Signature made Fri 17 Aug 2018 19:29:22 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: fw_cfg: ignore suffixes in the bootdevice list dependent on machine class sysbus: always allow explicit_ofw_unit_address() to override address generation machine: Fix coding style at machine_run_board_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-17Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20180817.0' ↵Peter Maydell
into staging VFIO update 2018-08-17 - Enhance balloon inhibitor for multiple users and use around vfio device assignment (Alex Williamson) # gpg: Signature made Fri 17 Aug 2018 17:43:37 BST # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-update-20180817.0: vfio/ccw/pci: Allow devices to opt-in for ballooning vfio: Inhibit ballooning based on group attachment to a container kvm: Use inhibit to prevent ballooning without synchronous mmu balloon: Allow multiple inhibit users Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-17vfio/ccw/pci: Allow devices to opt-in for ballooningAlex Williamson
If a vfio assigned device makes use of a physical IOMMU, then memory ballooning is necessarily inhibited due to the page pinning, lack of page level granularity at the IOMMU, and sufficient notifiers to both remove the page on balloon inflation and add it back on deflation. However, not all devices are backed by a physical IOMMU. In the case of mediated devices, if a vendor driver is well synchronized with the guest driver, such that only pages actively used by the guest driver are pinned by the host mdev vendor driver, then there should be no overlap between pages available for the balloon driver and pages actively in use by the device. Under these conditions, ballooning should be safe. vfio-ccw devices are always mediated devices and always operate under the constraints above. Therefore we can consider all vfio-ccw devices as balloon compatible. The situation is far from straightforward with vfio-pci. These devices can be physical devices with physical IOMMU backing or mediated devices where it is unknown whether a physical IOMMU is in use or whether the vendor driver is well synchronized to the working set of the guest driver. The safest approach is therefore to assume all vfio-pci devices are incompatible with ballooning, but allow user opt-in should they have further insight into mediated devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17vfio: Inhibit ballooning based on group attachment to a containerAlex Williamson
We use a VFIOContainer to associate an AddressSpace to one or more VFIOGroups. The VFIOContainer represents the DMA context for that AdressSpace for those VFIOGroups and is synchronized to changes in that AddressSpace via a MemoryListener. For IOMMU backed devices, maintaining the DMA context for a VFIOGroup generally involves pinning a host virtual address in order to create a stable host physical address and then mapping a translation from the associated guest physical address to that host physical address into the IOMMU. While the above maintains the VFIOContainer synchronized to the QEMU memory API of the VM, memory ballooning occurs outside of that API. Inflating the memory balloon (ie. cooperatively capturing pages from the guest for use by the host) simply uses MADV_DONTNEED to "zap" pages from QEMU's host virtual address space. The page pinning and IOMMU mapping above remains in place, negating the host's ability to reuse the page, but the host virtual to host physical mapping of the page is invalidated outside of QEMU's memory API. When the balloon is later deflated, attempting to cooperatively return pages to the guest, the page is simply freed by the guest balloon driver, allowing it to be used in the guest and incurring a page fault when that occurs. The page fault maps a new host physical page backing the existing host virtual address, meanwhile the VFIOContainer still maintains the translation to the original host physical address. At this point the guest vCPU and any assigned devices will map different host physical addresses to the same guest physical address. Badness. The IOMMU typically does not have page level granularity with which it can track this mapping without also incurring inefficiencies in using page size mappings throughout. MMU notifiers in the host kernel also provide indicators for invalidating the mapping on balloon inflation, not for updating the mapping when the balloon is deflated. For these reasons we assume a default behavior that the mapping of each VFIOGroup into the VFIOContainer is incompatible with memory ballooning and increment the balloon inhibitor to match the attached VFIOGroups. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson
Remove KVM specific tests in balloon_page(), instead marking ballooning as inhibited without KVM_CAP_SYNC_MMU support. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17balloon: Allow multiple inhibit usersAlex Williamson
A simple true/false internal state does not allow multiple users. Fix this within the existing interface by converting to a counter, so long as the counter is elevated, ballooning is inhibited. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell
into staging x86 queue, 2018-08-16 Bug fix: * Some guests may crash when using "-cpu host" due to TOPOEXT, disable it by default Features: * PV_SEND_IPI feature bit * Icelake-{Server,Client} CPU models * New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES Documentation: * docs/qemu-cpu-models.texi # gpg: Signature made Fri 17 Aug 2018 02:33:09 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Disable TOPOEXT by default on "-cpu host" target-i386: adds PV_SEND_IPI CPUID feature bit i386: Add new CPU model Icelake-{Server,Client} i386: Add CPUID bit for WBNOINVD i386: Add CPUID bit for PCONFIG i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES docs: add guidance on configuring CPU models for x86 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16fw_cfg: ignore suffixes in the bootdevice list dependent on machine classMark Cave-Ayland
For the older machines (such as Mac and SPARC) the DT nodes representing bootdevices for disk nodes are irregular for mainly historical reasons. Since the majority of bootdevice nodes for these machines either do not have a separate disk node or require different (custom) names then it is much easier for processing to just disable all suffixes for a particular machine. Introduce a new ignore_boot_device_suffixes MachineClass property to control bootdevice suffix generation, defaulting to false in order to preserve compatibility. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20180810124027.10698-1-mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16sysbus: always allow explicit_ofw_unit_address() to override address generationMark Cave-Ayland
Some SysBusDevices either use sysbus_init_mmio() without sysbus_mmio_map() or the first MMIO memory region doesn't represent the bus address, causing a firmware device path with an invalid address to be generated. SysBusDeviceClass does provide a virtual explicit_ofw_unit_address() method that can be used to override this process, but it was originally intended only as as a fallback option meaning that any existing MMIO memory regions still take priority whilst determining the firmware device address. There is currently only one user of explicit_ofw_unit_address() and that is the PCI expander bridge (PXB) device which has no MMIO/PIO resources defined. This enables us to allow explicit_ofw_unit_address() to take priority without affecting backwards compatibility, allowing the address to be customised as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20180805112850.26063-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16machine: Fix coding style at machine_run_board_init()Dou Liyang
Commit 7747abf11487 ("hw/machine: Remove the Zero check of nb_numa_nodes for numa_complete_configuration()") removed the curly brackets. Re-add them. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <20180710105129.23296-1-douly.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [ehabkost: rewrote commit message] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' ↵Peter Maydell
into staging MIPS queue Aug 16, 2018 # gpg: Signature made Thu 16 Aug 2018 18:19:36 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: qemu-doc: Amend MIPS-related items linux-user: Add preprocessor availability control to some syscalls linux-user: Update MIPS syscall numbers up to kernel 4.18 headers elf: Add ELF flags for MIPS machine variants elf: Remove duplicate preprocessor constant definition target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 target/mips: Don't update BadVAddr register in Debug Mode target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add CP0 BadInstrX register target/mips: Update some CP0 registers bit definitions target/mips: Fix two instances of shadow variables target/mips: Mark switch fallthroughs with interpretable comments target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Avoid case statements formulated by ranges - part 1 MAINTAINERS: Update target/mips maintainer's email addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16qemu-doc: Amend MIPS-related itemsAleksandar Markovic
Amend MIPS-related items in qemu-doc.texi Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Add preprocessor availability control to some syscallsAleksandar Rikalo
Add ability to target platforms to individually include user-mode support for system calls from "stat" group of system calls. This change is related to new nanoMIPS platform in the sense that it supports a different set of "stat" system calls than any other target. nanoMIPS does not support structures stat and stat64 at all. Also, support for certain number of other system calls is dropped in nanoMIPS (those are most of the time obsoleted system calls). Without this patch, build for nanoMIPS would fail. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Update MIPS syscall numbers up to kernel 4.18 headersAleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 9 new syscall numbers, the last being NR_io_pgetevents. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Add ELF flags for MIPS machine variantsAleksandar Markovic
Add MIPS machine variants ELF flags so that the emulation behavior can be adjusted if needed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16elf: Remove duplicate preprocessor constant definitionAleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH. The duplicate was introduced in commit 45506bdd. It placed the constant EF_MIPS_ARCH in a better place, however it did not remove the original. This patch removes the original occurrence. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is set. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Implement CP0 Config1.WR bit functionalityStefan Markovic
Add testing Config1.WR bit into watch exception handling logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Add CP0 BadInstrX registerStefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Update some CP0 registers bit definitionsAleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3, Config4, and Config5 bit definitions. Some of these bits will be utilized by upcoming nanoMIPS changes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Fix two instances of shadow variablesAleksandar Markovic
Fix two instances of shadow variables. This cleans up entire file translate.c from shadow variables. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Mark switch fallthroughs with interpretable commentsAleksandar Markovic
Mark switch fallthroughs with comments, in cases fallthroughs are intentional. The comments "/* fall through */" are interpreted by compilers and other tools, and they will not issue warnings in such cases. For gcc, the warning is turnend on by -Wimplicit-fallthrough. With this patch, there will be no such warnings in target/mips directory. If such warning appears in future, it should be checked if it is intentional, and, if yes, marked with a comment similar to those from this patch. The comment must be just before next "case", otherwise gcc won't understand it. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 2Aleksandar Rikalo
Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 1Aleksandar Markovic
Remove "range style" case statements to make code analysis easier. This is needed also for some upcoming nanoMIPS-related refactorings. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16MAINTAINERS: Update target/mips maintainer's email addressesAleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the MAINTAINERS file. Also, add corresponding items in the .mailmap file. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16i386: Disable TOPOEXT by default on "-cpu host"Eduardo Habkost
Enabling TOPOEXT is always allowed, but it can't be enabled blindly by "-cpu host" because it may make guests crash if the rest of the cache topology information isn't provided or isn't consistent. This addresses the bug reported at: https://bugzilla.redhat.com/show_bug.cgi?id=1613277 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180809221852.15285-1-ehabkost@redhat.com> Tested-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: Babu Moger <babu.moger@amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16target-i386: adds PV_SEND_IPI CPUID feature bitWanpeng Li
Adds PV_SEND_IPI CPUID feature bit. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1530526971-1812-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add new CPU model Icelake-{Server,Client}Robert Hoo
New CPU models mostly inherit features from ancestor Skylake, while addin new features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD, AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG), Intel PT and 5-level paging (Server only). As well as IA32_PRED_CMD, SSBD support for speculative execution side channel mitigations. Note: For 5-level paging, Guest physical address width can be configured, with parameter "phys-bits". Unless explicitly specified, we still use its default value, even for Icelake-Server cpu model. At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR actually presents more than 1 'feature', maintainers are considering expanding current features presentation of only CPUIDs to MSR bits; 2) a reasonable default value for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully beyond Icelake CPU model itself but fundamental. So split these work apart and do it later. https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-6-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit for WBNOINVDRobert Hoo
WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-5-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit for PCONFIGRobert Hoo
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSRRobert Hoo
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIESRobert Hoo
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16docs: add guidance on configuring CPU models for x86Daniel P. Berrangé
With the recent set of CPU hardware vulnerabilities on x86, it is increasingly difficult to understand which CPU configurations are good to use and what flaws they might be vulnerable to. This doc attempts to help management applications and administrators in picking sensible CPU configuration on x86 hosts. It outlines which of the named CPU models are good choices, and describes which extra CPU flags should be enabled to allow the guest to mitigate hardware flaws. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20180627160103.13634-1-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180816' into staging target-arm queue: * Fixes for various bugs in SVE instructions * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board * hw/arm: make bitbanded IO optional on ARMv7-M * Add model of Cortex-M0 CPU * Add support for loading Intel HEX files to the generic loader * imx_spi: Unset XCH when TX FIFO becomes empty * aspeed_sdmc: fix various bugs * Fix bugs in Arm FP16 instruction support * Fix aa64 FCADD and FCMLA decode * softfloat: Fix missing inexact for floating-point add * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() # gpg: Signature made Thu 16 Aug 2018 14:33:41 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits) hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() softfloat: Fix missing inexact for floating-point add target/arm: Fix aa64 FCADD and FCMLA decode target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h target/arm: Ignore float_flag_input_denormal from fp_status_f16 target/arm: Adjust FPCR_MASK for FZ16 aspeed: add a max_ram_size property to the memory controller aspeed_sdmc: Handle ECC training aspeed_sdmc: Init status always idle aspeed_sdmc: Set 'cache initial sequence' always true aspeed_sdmc: Fix saved values aspeed_sdmc: Extend number of valid registers imx_spi: Unset XCH when TX FIFO becomes empty Add QTest testcase for the Intel Hexadecimal loader: Implement .hex file loader loader: add rom transaction API loader: extract rom_free() function target/arm: add "cortex-m0" CPU model hw/arm: make bitbanded IO optional on ARMv7-M ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()Thomas Huth
Now that we've got the common sysbus_init_child_obj() function, we do not need the local init_sysbus_child() anymore. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16softfloat: Fix missing inexact for floating-point addRichard Henderson
For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15 we dropped the sticky bit and so failed to raise inexact. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Fix aa64 FCADD and FCMLA decodeRichard Henderson
These insns require u=1; failed to include that in the switch cases. This probably happened during one of the rebases just before final commit. Fixes: d17b7cdcf4e Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-halfRichard Henderson
We were using the wrong flush-to-zero bit for the non-half input. Fixes: 46d33d1e3c9 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_hRichard Henderson
This makes float16_muladd correctly use FZ16 not FZ. Fixes: 6ceabaad110 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Ignore float_flag_input_denormal from fp_status_f16Richard Henderson
When FZ is set, input_denormal exceptions are recognized, but this does not happen with FZ16. The softfloat code has no way to distinguish these bits and will raise such exceptions into fp_status_f16.flags, so ignore them when computing the accumulated flags. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16target/arm: Adjust FPCR_MASK for FZ16Richard Henderson
When support for FZ16 was added, we failed to include the bit within FPCR_MASK, which means that it could never be set. Continue to zero FZ16 when ARMv8.2-FP16 is not enabled. Fixes: d81ce0ef2c4 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180810193129.1556-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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