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2018-02-13hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheetPhilippe Mathieu-Daudé
checking Xilinx datasheet "UG1085" (v1.7) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-27-f4bug@amsat.org>
2018-02-13hw/arm/fsl-imx6: implement SDHCI Spec. v3Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-26-f4bug@amsat.org>
2018-02-13hw/arm/bcm2835_peripherals: change maximum block size to 1kBPhilippe Mathieu-Daudé
following the datasheet. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-25-f4bug@amsat.org>
2018-02-13hw/arm/bcm2835_peripherals: implement SDHCI Spec v3Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-24-f4bug@amsat.org>
2018-02-13sdhci: implement CMD/DAT[] fields in the Present State registerPhilippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-23-f4bug@amsat.org>
2018-02-13sdhci: implement UHS-I voltage switchPhilippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-22-f4bug@amsat.org>
2018-02-13sdbus: add trace eventsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-21-f4bug@amsat.org>
2018-02-13sdhci: implement the Host Control 2 register (tuning sequence)Philippe Mathieu-Daudé
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-20-f4bug@amsat.org>
2018-02-13sdhci: rename the hostctl1 registerPhilippe Mathieu-Daudé
As per the Spec v3.00 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-19-f4bug@amsat.org>
2018-02-13sdhci: add support for v3 capabilitiesPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-18-f4bug@amsat.org>
2018-02-13hw/arm/xilinx_zynq: fix the capabilities register to match the datasheetPhilippe Mathieu-Daudé
checking Xilinx datasheet "UG585" (v1.12.1) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-17-f4bug@amsat.org>
2018-02-13hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2)Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-16-f4bug@amsat.org>
2018-02-13hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64()Philippe Mathieu-Daudé
We only set a 32-bit value, but this is a good practice in case this code is used as reference. (missed in 5efc9016e52) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-15-f4bug@amsat.org>
2018-02-13sdhci: check Spec v2 capabilities (DMA and 64-bit bus)Philippe Mathieu-Daudé
Incorrect value will throw an error. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-14-f4bug@amsat.org>
2018-02-13sdhci: Fix 64-bit ADMA2Sai Pavan Boddu
The 64-bit ADMA address is not converted to the cpu endianes correctly. This patch fixes the issue and uses a valid mask for the attribute data. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> [AF: Re-write commit message] Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-13-f4bug@amsat.org>
2018-02-13sdhci: replace DMA magic value by BLOCK_SIZE_MASKPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-12-f4bug@amsat.org>
2018-02-13sdhci: check the Spec v1 capabilities correctnessPhilippe Mathieu-Daudé
Incorrect value will throw an error. Note than Spec v2 is supported by default. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-11-f4bug@amsat.org>
2018-02-13sdhci: simplify sdhci_get_fifolen()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-10-f4bug@amsat.org>
2018-02-13sdhci: use a numeric value for the default CAPAB registerPhilippe Mathieu-Daudé
using many #defines is not portable when scaling to different HCI. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-9-f4bug@amsat.org>
2018-02-13sdhci: add a 'spec_version property' (default to v2)Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-8-f4bug@amsat.org>
2018-02-13sdhci: add qtest to check the SD Spec versionPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20180208164818.7961-7-f4bug@amsat.org>
2018-02-13sdhci: add a check_capab_sdma() qtestPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20180208164818.7961-6-f4bug@amsat.org>
2018-02-13sdhci: add a check_capab_baseclock() qtestPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20180208164818.7961-5-f4bug@amsat.org>
2018-02-13sdhci: add check_capab_readonly() qtestPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20180208164818.7961-4-f4bug@amsat.org>
2018-02-13sdhci: add qtest to check the SD capabilities registerPhilippe Mathieu-Daudé
The PCI model is tested with the pc/x86_64 machine, the SysBus model with the smdkc210/arm machine. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20180208164818.7961-3-f4bug@amsat.org>
2018-02-13sdhci: use error_propagate(local_err) in realize()Philippe Mathieu-Daudé
avoid the "errp && *errp" pattern (not recommended in "qapi/error.h" comments). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-2-f4bug@amsat.org>
2018-02-13build-sys: check static linking of UBSANMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180208162343.30809-2-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13build-sys: remove useless extra*flags variablesMarc-André Lureau
Only EXTRA_LDFLAGS seems to be used during configure Xen checks. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180208162343.30809-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hw/net/can: interrupt cleanupPaolo Bonzini
Define two functions to update the interrupt state, and call them on loadvm. This removes the need to migrate the state as part of vmstate_kvaser_pci. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13net/can: documentationPavel Pisa
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hw/net/can: MIOe-3680 PCI (dual SJA1000 channel) emulationDeniz Eren
Signed-off-by: Deniz Eren <deniz.eren@icloud.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hw/net/can: PCM-3680I PCI (dual SJA1000 channel) emulationDeniz Eren
Signed-off-by: Deniz Eren <deniz.eren@icloud.com> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hw/net/can: Kvaser PCI CAN-S (single SJA1000 channel) emulationPavel Pisa
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hw/net/can: SJA1000 chip register level emulation for QEMUPavel Pisa
The core SJA1000 support is independent of following patches which map SJA1000 chip to PCI boards. The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13net/can: support for connecting to Linux host SocketCAN interface.Pavel Pisa
Connection to the real host CAN bus network through SocketCAN network interface is available only for Linux host system. Mechanism is generic, support for another CAN API and operating systems can be implemented in future. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13net/can: simple messages transport implementation for QEMUPavel Pisa
The CanBusState state structure is created for each emulated CAN channel. Individual clients/emulated CAN interfaces or host interface connection registers to the bus by CanBusClientState structure. The CAN core is prepared to support connection to the real host CAN bus network. The commit with such support for Linux SocketCAN follows. Implementation is as simple as possible. There is no state to be migrated, and messages prioritization and queuing are not considered for now. But it is intended to be extended when need arises. Development repository and more documentation at https://gitlab.fel.cvut.cz/canbus/qemu-canbus The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13hax: Support guest RAM sizes of 4GB or moreYu Ning
Since HAX_VM_IOCTL_ALLOC_RAM takes a 32-bit size, it cannot handle RAM blocks of 4GB or larger, which is why HAXM can only run guests with less than 4GB of RAM. Solve this problem by utilizing the new HAXM API, HAX_VM_IOCTL_ADD_RAMBLOCK, which takes a 64-bit size, to register RAM blocks with the HAXM kernel module. The new API is first added in HAXM 7.0.0, and its availablility and be confirmed by the presence of the HAX_CAP_64BIT_RAMBLOCK capability flag. When the guest RAM size reaches 7GB, QEMU will ask HAXM to set up a memory mapping that covers a 4GB region, which will fail, because HAX_VM_IOCTL_SET_RAM also takes a 32-bit size. Work around this limitation by splitting the large mapping into small ones and calling HAX_VM_IOCTL_SET_RAM multiple times. Bug: https://bugs.launchpad.net/qemu/+bug/1735576 Signed-off-by: Yu Ning <yu.ning@intel.com> Message-Id: <1515752555-12784-1-git-send-email-yu.ning@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13make: fix help message reference to bogus V=0 variableDaniel P. Berrange
The make rules for building QEMU are mostly silent by default. They can be made verbose by setting the variable V=1. The default state does not however correspond to a V=0 setting - $(V) must be undefined / empty to get the default quiet build. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <20180123164718.12714-3-berrange@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-13Revert "build-sys: silence make by default or V=0"Daniel P. Berrange
This reverts commit 42a77f1ce4934b243df003f95bda88530631387a. The primary intention of this change was to silence messages like make[1]: '/home/berrange/src/virt/qemu/capstone/libcapstone.a' is up to date. which we get when calling make recursively with explicit targets. The problem is that this change affected every make target, not merely the targets that triggered these "is up to date" messages. As a result any targets that were not invoking commands via "$(call quiet-command ...)" suddenly become silent. This is particularly bad for "make install" which now appears todo nothing. Rather than go through every make rule and try to identify places where we now need to explicitly print a message to show work taking place, just revert the change. To address the original problem of silencing "is up to date" messages, we simply add --quiet to the SUBDIR_MAKEVARS variable, so it only affects us on recursive make calls. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <20180123164718.12714-2-berrange@redhat.com> Tested-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-12Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180212' ↵Peter Maydell
into staging ppc patch queue 2018-02-12 Here's the accumulatead ppc and pseries related patches for the last while. Highlights are: * A number of Macintosh / CUDA cleanups from Mark Cave-Ayland * An important bug fix (missing "break;") for H_GET_CPU_CHARACTERISTICS * Yet another fix for SMT mode handling * Assorted other cleanups and fixes # gpg: Signature made Mon 12 Feb 2018 03:39:30 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180212: misc: introduce new mos6522 VIA device and enable it for ppc builds cuda: factor out timebase-derived counter value and load time cuda: set timer 1 frequency property to CUDA_TIMER_FREQ cuda: don't call cuda_update() when writing to ACR register cuda: minor cosmetic tidy-ups to get_next_irq_time() cuda: rename frequency property to tb_frequency cuda: introduce CUDAState parameter to get_counter() spapr: set vsmt to MAX(8, smp_threads) cuda: don't allow writes to port output pins cuda: do not use old_mmio accesses hw/ppc: rename functions in comments spapr: add missing break in h_get_cpu_characteristics() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-12Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into ↵Peter Maydell
staging trivial patches for 2018-02-10 # gpg: Signature made Sat 10 Feb 2018 07:54:03 GMT # gpg: using RSA key 701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * remotes/mjt/tags/trivial-patches-fetch: tests/qapi: use ARRAY_SIZE macro tests/qapi: use QEMU_IS_ALIGNED macro tests/hbitmap: use ARRAY_SIZE macro async: use ARRAY_SIZE macro qga: use ARRAY_SIZE macro MAINTAINERS: Add qemu-binfmt-conf.sh script oslib-posix: check for posix_memalign in configure script maint: Mention web site maintenance in README build: fix typo in error message configure: Allow capstone=git only if git update is not disabled scripts/make-release: Don't archive .git files qemu-options.hx: Remove confusing spaces in parameter listings mailmap: set preferred spelling for Daniel Berrangé Drop unneeded system header includes machine: Polish -machine xxx,help scripts/argparse.py: spelling (independant) qapi-schema.json: spelling (independant comparation) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-12Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-02-09' into ↵Peter Maydell
staging nbd patches for 2018-02-09 - Vladimir Sementsov-Ogievskiy: iotests: 205: support luks format - Eric Blake: block: Simplify bdrv_can_write_zeroes_with_unmap() # gpg: Signature made Fri 09 Feb 2018 18:34:20 GMT # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-02-09: block: Simplify bdrv_can_write_zeroes_with_unmap() iotests: 205: support luks format Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-11misc: introduce new mos6522 VIA device and enable it for ppc buildsMark Cave-Ayland
The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and including a conversion to trace-events. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: factor out timebase-derived counter value and load timeMark Cave-Ayland
Commit b981289c49 "PPC: Cuda: Use cuda timer to expose tbfreq to guest" altered the timer calculations from those based upon the hardware CUDA clock frequency to those based upon the CPU timebase frequency. In fact we can isolate the differences to 2 simple changes: one to the counter read value and another to the counter load time. Move these changes into separate functions so the implementation can be swapped later. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: set timer 1 frequency property to CUDA_TIMER_FREQMark Cave-Ayland
Now that we have successfully decoupled the timebase frequency and the hardware timer frequency, set the timer 1 frequency property to CUDA_TIMER_FREQ and alter get_next_irq_time() to use it rather than the hard-coded constant. In addition to this we must now switch the tb_diff calculation over to use the timebase frequency now that the hardware clock frequency and the timebase frequency are different. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [dwg: Correct a conflict due to a bug in an earlier patch] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: don't call cuda_update() when writing to ACR registerMark Cave-Ayland
The wire protocol for reading data to/from the VIA is triggered by changing inputs on port B rather than changing the timer configuration via the ACR. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: minor cosmetic tidy-ups to get_next_irq_time()Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: rename frequency property to tb_frequencyMark Cave-Ayland
This allows us to more easily differentiate between the timebase frequency used to calibrate the MacOS timers and the actual frequency of the hardware clock as indicated by CUDA_TIMER_FREQ. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [dwg: Revert some extraneous changes which break compile] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-11cuda: introduce CUDAState parameter to get_counter()Mark Cave-Ayland
This will be required shortly and also happens to match nicely with the corresponding signature for set_counter(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-10spapr: set vsmt to MAX(8, smp_threads)Laurent Vivier
We ignore silently the value of smp_threads when we set the default VSMT value, and if smp_threads is greater than VSMT kernel is going into trouble later. Fixes: 8904e5a750 ("spapr: Adjust default VSMT value for better migration compatibility") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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