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2011-03-10vmstate: be able to store/save a pci device from a pointerJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: Add a way to send a partial arrayJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: add VMSTATE_STRUCT_VARRAY_UINT32Juan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: add VMSTATE_INT64_ARRAYJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: add VMSTATE_STRUCT_VARRAY_INT32Juan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: add UINT32 VARRAYSJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: Fix varrays with uint8 indexesJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vmstate: add VMSTATE_UINT32_EQUALJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10vnc: Fix stack corruption and other bitmap related bugsStefan Weil
Commit bc2429b9174ac2d3c56b7fd35884b0d89ec7fb02 introduced a severe bug (stack corruption). bitmap_clear was called with a wrong argument which caused out-of-bound writes to the local variable width_mask. This bug was detected with QEMU running on windows. It also occurs with wine: *** stack smashing detected ***: terminated wine: Unhandled illegal instruction at address 0x6115c7 (thread 0009), starting debugger... The bug is not windows specific! Instead of fixing the wrong parameter value, bitmap_clear(), bitmap_set and width_mask were removed, and bitmap_intersect() was replaced by !bitmap_empty(). The new operation is much shorter and equivalent to the old operations. The declarations of the dirty bitmaps in vnc.h were also wrong for 64 bit hosts because of a rounding effect: for these hosts, VNC_MAX_WIDTH is no longer a multiple of (16 * BITS_PER_LONG), so the rounded value of VNC_DIRTY_WORDS was too small. Fix both declarations by using the macro which is designed for this purpose. Cc: Corentin Chary <corentincj@iksaif.net> Cc: Wen Congyang <wency@cn.fujitsu.com> Cc: Gerhard Wiesinger <lists@wiesinger.com> Cc: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10hmp-commands.hx: fix badly merged client_migrate_info commandJes Sorensen
client_migrate_info was merged badly, placing it between the command and the documentation for another command. In addition it did not respect the general rule of hmp-commands.hx, of having command definition before the documentation. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10Fix performance regression in qemu_get_ram_ptrVincent Palatin
When the commit f471a17e9d869df3c6573f7ec02c4725676d6f3a converted the ram_blocks structure to QLIST, it also removed the conditional check before switching the current block at the beginning of the list. In the common use case where ram_blocks has a few blocks with only one frequently accessed (the main RAM), this has a performance impact as it performs the useless list operations on each call (which are on a really hot path). On my machine emulation (ARM on amd64), this patch reduces the percentage of CPU time spent in qemu_get_ram_ptr from 6.3% to 2.1% in the profiling of a full boot. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-10xilinx-ethlite: Simplify byteswapping to/from bramsEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
2011-03-10mainstone: PCMCIA supportDmitry Eremin-Solenikov
Extend mst_fpga and mainstone with logic to support PCMCIA attachment (IRQs, status regs). Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-10mainstone: use gpio 0 for connection of FPGA instead of hooking into PIC ↵Dmitry Eremin-Solenikov
directly Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-10pxa2xx_timer: Get rid of .level in PXA2xxTimer0.Andrzej Zaborowski
2011-03-10pxa2xx_pic: fixup initialisationAndrzej Zaborowski
This is based on Dmitry Eremin-Solenikov's patch but simplified.
2011-03-10pxa2xx_timer: separate irq for pxa27x handlingDmitry Eremin-Solenikov
First, sysbus_init_irq shan't be called on on-stack variables. Indeed, it only stores a passed pointer in qdev and the stored irq is later populated, so we get a nice write-to-stack bug. Second, irq for pxa27x should probably be handled in a more gentler way, as we should check if we have events to raise this irq. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-03-07MAINTAINERS: add LatticeMico32 maintainerMichael Walle
Add me as the lm32-target and machines maintainer. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07Add lm32 target to configureMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: opcode testsuiteMichael Walle
This patch creates tests/lm32 directory and adds tests for every LatticeMico32 opcode. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: todo and documentationMichael Walle
This patch adds general target documentation and a todo list. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: EVR32 and uclinux BSPMichael Walle
This patch adds support for the following two BSPs: - LM32 EVR32 BSP (as used by RTEMS) - uclinux BSP by Theobroma Systems Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: support for creating device treeMichael Walle
This patch adds helper functions to create a ROM, which contains a hardware description of a board. This is used in Theobromas LM32 Linux port. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: system control modelMichael Walle
This patch add support for a system control block. It is supposed to act as helper for the emulated program. E.g. shutting down the VM or printing test results. This model is intended for testing purposes only and doesn't fit to any real hardware. Therefore, it is not added to any board by default. Instead a user has to add it explicitly with the '-device' commandline parameter. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: uart modelMichael Walle
This patch add support for the LatticeMico32 UART. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: timer modelMichael Walle
This patch adds support for the LatticeMico32 system timer. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: pic and juart helper functionsMichael Walle
This patch adds init functions for the PIC and JTAG UART commonly used in the board initialization. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: juart modelMichael Walle
This patch adds the JTAG UART model. It is accessed through special control registers and opcodes. Therefore the translation uses callbacks to this model. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: interrupt controller modelMichael Walle
This patch adds the interrupt controller of the lm32. Because the PIC is accessed through special control registers and opcodes, there are callbacks from the lm32 translation code to this model. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: gdbstub supportMichael Walle
This patch adds lm32 support to the gdbstub. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: machine state loading/savingMichael Walle
This patch adds support for saving and loading the processor state. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: translation code helperMichael Walle
This patch adds translation helper functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07lm32: translation routinesMichael Walle
This patch adds the main translation routine. All opcodes of the LatticeMico32 processor are supported and translated to TCG ops. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07LatticeMico32 target supportMichael Walle
This patch adds support for the LatticeMico32 softcore processor by Lattice Semiconductor. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-03-07target-arm: Implement a minimal set of cp14 debug registersPeter Maydell
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Use TCG temporary leak debugging facilitiesPeter Maydell
Use the new TCG temporary leak debugging facilities to check that each ARM instruction does not leak temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Remove ad-hoc leak checking codePeter Maydell
This commit removes the ad-hoc resource leak checking code from target-arm. This includes replacing all uses of new_tmp() with tcg_temp_new_i32() and all uses of dead_tmp() with tcg_temp_free_i32(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07tcg: Add support for debugging leakage of temporariesPeter Maydell
Add support (if CONFIG_DEBUG_TCG is defined) for debugging leakage of temporary variables. Generally any temporaries created by a target while it is translating an instruction should be freed by the end of that instruction; otherwise carefully crafted guest code could cause TCG to run out of temporaries and assert. By calling tcg_check_temp_count() after each instruction we can check that we are not leaking temporaries in this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Integrate secondary CPU reset in arm_bootAdam Lackorzynski
Integrate secondary CPU reset into arm_boot, removing it from realview.c. On non-Linux systems secondary CPUs start with the same entry as the boot CPU. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski
Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Fix soft interrupt in GIC distributorAdam Lackorzynski
Fix selection of target list filter mode. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Set carry flag correctly for Thumb2 ORNSPeter Maydell
The code for Thumb2 ORNS (or negated and set flags) was trashing a TCG input register which was needed later for use in calculating flags, with the effect that the carry flag was always set with the wrong sense. Fix this by using the TCG orc op instead of separate not and or ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06ioport: Improve error outputAndreas Färber
When failing due to conflicting I/O port registrations, include the offending I/O port address in the message. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06tracetool: Add optional argument to specify dtrace probe namesJes Sorensen
Optional feature allowing a user to generate the probe list to match the name of the binary, in case they wish to install qemu under a different name than qemu-{system,user},<arch> Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Stefan Hajnoczi <stefaha@linux.vnet.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Handle VMOV between two core and VFP single regsPeter Maydell
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a pair of VFP single precision registers): * An incorrect condition meant these instruction patterns were being treated as load/store multiple, which resulted in the generation of bad code and a runtime segfault * The order of the core register pair was reversed so the values would go to the wrong registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06w32: Add support for cursesStefan Weil
MinGW optionally includes pdcurses, so add support for it. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Don't decode old cp15 WFI instructions on v7 coresPeter Maydell
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class instruction, but in previous versions this functionality was provided via a cp15 coprocessor register. Add correct feature checks to the decoding of the cp15 WFI instructions so that they behave correctly for newer cores. In particular, the old 0,c7,c8,2 encoding used on ARM940 has been reused for VA-to-PA translation in v6 and v7. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06net: Add the missing option declaration of "vhostforce"Jason Wang
Signed-off-by: Jason Wang <jasowang@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06gt64xxx: remove savevm supportJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06vmstate: remove uninorth savevm codeJuan Quintela
It was migrating the wrong structures, no way it would work Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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