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2014-03-18Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-2' into stagingPeter Maydell
vnc: fix vmware VGA incompatiblities # gpg: Signature made Tue 18 Mar 2014 07:23:10 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vnc-2: ui/vnc: fix vmware VGA incompatiblities Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-18acpi: fix endian-ness for table idsMichael S. Tsirkin
when using signature for table ID, we forgot to byte-swap it. signatures are really ASCII strings, let's treat them as such. While at it, get rid of most of _SIGNATURE macros. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi-test: signature endian-ness fixesMichael S. Tsirkin
acpi table signature is really an ASCII string. Treat it as such in tests. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140317' into staging target-arm queue: * more A64 Neon instructions * fixes to reset CBAR values for A9 and A15 boards * fix accesses to PMCR register in -icount mode # gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits) scripts/qemu-binfmt-conf.sh: Add AArch64 registration target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) target-arm: A64: Implement FCVTXN target-arm: A64: Implement scalar saturating narrow ops target-arm: A64: Move handle_2misc_narrow function target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE softfloat: export squash_input_denormal functions target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder target-arm: A64: Implement FRINT* target-arm: A64: Implement SRI target-arm: A64: Add FRECPX (reciprocal exponent) target-arm: A64: List unsupported shift-imm opcodes target-arm: A64: Implement FCVTL target-arm: A64: Implement FCVTN target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions target-arm: A64: Implement SHLL, SHLL2 target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP target-arm: A64: Saturating and narrowing shift ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-18i386/acpi-build: support hotplug of VCPU with APIC ID 0xFFLaszlo Ersek
Building on the previous patch, raise the maximal count of processor objects / NTFY branches / CPON elements from 255 to 256. This allows the VCPU with APIC ID 0xFF to be hotplugged. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi-test: rebuild SSDTMichael S. Tsirkin
commit 9bcc80cd71892df42605e0c097d85c0237ff45d1 i386/acpi-build: allow more than 255 elements in CPON Replaces 0x1 with a smaller One constant. rebuild expected SSDT. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18i386/acpi-build: allow more than 255 elements in CPONLaszlo Ersek
The build_ssdt() function builds a number of AML objects that are related to CPU hotplug, and whose IDs form a contiguous sequence of APIC IDs. (APIC IDs are in fact discontiguous, but this is the traditional interface: build a contiguous sequence from zero up that covers all possible APIC IDs.) These objects are: - a Processor() object for each VCPU, - a NTFY method, with one branch for each VCPU, - a CPON package with one element (hotplug status byte) for each VCPU. The build_ssdt() function currently limits the *count* of processor objects, and NTFY branches, and CPON elements, in 0xFF (see the assignment to "acpi_cpus"). This allows for an inclusive APIC ID range of [0..254]. This is incorrect, because the highest APIC ID that we otherwise allow a VCPU to take is 255. In order to extend the maximum count to 256, and the traversed APIC ID range correspondingly to [0..255]: - the Processor() objects need no change, - the NTFY method also needs no change, - the CPON package must be updated, because it is defined with a DefPackage, and the number of elements in such a package can be at most 255. We pick a DefVarPackage instead. We replace the Op byte, and the encoding of the number of elements. Compare: DefPackage := PackageOp PkgLength NumElements PackageElementList DefVarPackage := VarPackageOp PkgLength VarNumElements PackageElementList PackageOp := 0x12 VarPackageOp := 0x13 NumElements := ByteData VarNumElements := TermArg => Integer The build_append_int() function implements precisely the following TermArg encodings (a subset of what the ACPI spec describes): TermArg := DataObject DataObject := ComputationalData ComputationalData := ConstObj | ByteConst | WordConst | DWordConst directly encoded in the function, with build_append_byte(): ConstObj := ZeroOp | OneOp ZeroOp := 0x00 OneOp := 0x01 call to build_append_value(..., 1): ByteConst := BytePrefix ByteData BytePrefix := 0x0A ByteData := 0x00 - 0xFF call to build_append_value(..., 2): WordConst := WordPrefix WordData WordPrefix := 0x0B WordData := ByteData[0:7] ByteData[8:15] call to build_append_value(..., 4): DWordConst := DWordPrefix DWordData DWordPrefix := 0x0C DWordData := WordData[0:15] WordData[16:31] Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18pc: Refuse max_cpus if it results in too large APIC IDEduardo Habkost
This changes the PC initialization code to reject max_cpus if it results in an APIC ID that's too large, instead of aborting or erroring out when it is already too late. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi: Don't use MAX_CPUMASK_BITS for APIC ID bitmapEduardo Habkost
MAX_CPUMASK_BITS is a limit for max_cpus and CPU indexes, not for APIC IDs. ACPI_CPU_HOTPLUG_ID_LIMIT is the right macro for the limit on APIC IDs on the ACPI and CPU hotplug code. There are no functional changes introduced by this patch, as MAX_CPUMASK_BITS + 1 == 255 + 1 == 256 == ACPI_CPU_HOTPLUG_ID_LIMIT. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi: Assert sts array limit on AcpiCpuHotplug_add()Eduardo Habkost
AcpiCpuHotplug_add() can't handle vCPU arch IDs larger than ACPI_CPU_HOTPLUG_ID_LIMIT. Instead of corrupting memory in case the vCPU ID is too large, use g_assert() to ensure we are not over the limit. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18pc: Refuse CPU hotplug if the resulting APIC ID is too largeEduardo Habkost
The ACPI CPU hotplug code requires APIC IDs to be smaller than ACPI_CPU_HOTPLUG_ID_LIMIT, so enforce the limit before trying to hotplug a new vCPU, returning an error instead of crashing. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi: Add ACPI_CPU_HOTPLUG_ID_LIMIT macroEduardo Habkost
The new macro will be helpful to allow us to detect too large SMP limits before it is too late. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18acpi-test: update expected SSDT filesMichael S. Tsirkin
commit 13f65b2e1073cf7e2c8fb3880c77d8a53fa2f95e acpi-test: update expected SSDT files set an incorrect SSDT. rebuild it. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-18ui/vnc: fix vmware VGA incompatiblitiesPeter Lieven
this fixes invalid rectangle updates observed after commit 12b316d with the vmware VGA driver. The issues occured because the server and client surface update seems to be out of sync at some points and the max width of the surface is not dividable by VNC_DIRTY_BITS_PER_PIXEL (16). Reported-by: Serge Hallyn <serge.hallyn@ubuntu.com> Signed-off-by: Peter Lieven <pl@kamp.de> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-17Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140317' ↵Peter Maydell
into staging 4 small patches: - Fixing findings of valgrind regarding minor memory leaks: Currently we forget the pointer of qemu_allocate_irqs. Since we never free the irqs, this is not critical, but obviously not good programming style. While we are at it, we dont need the irq infrastructure for the sclp consoles. - Handle new ELF error codes for BIOS loading # gpg: Signature made Mon 17 Mar 2014 21:34:12 GMT using RSA key ID B5A61C7C # gpg: Can't check signature: public key not found * remotes/borntraeger/tags/kvm-s390-20140317: s390x/sclpconsole-lm: Fix and simplify irq setup s390x/sclpconsole: Fix and simplify interrupt injection s390x/cpu hotplug: Fix memory leak s390/ipl: Fix error path on BIOS loading Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17Merge remote-tracking branch 'remotes/rth/tcg-v8p-2' into stagingPeter Maydell
* remotes/rth/tcg-v8p-2: tcg-sparc: Convert to new ldst opcodes tcg-sparc: Convert to new ldst helpers tcg-sparc: Tidy tcg_out_tlb_load interface tcg-sparc: Use TCGMemOp within qemu_ldst routines tcg-sparc: Improve tcg_out_movi tcg-sparc: Dont handle constant arguments to ext32 ops tcg-sparc: Don't handle remainder tcg-sparc: Use intptr_t as appropriate tcg-sparc: Tidy call+jump patterns tcg-sparc: Fix tlb read tcg-sparc: Fix ld64 for 32-bit mode Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17s390x/sclpconsole-lm: Fix and simplify irq setupChristian Borntraeger
valgrind complains about a memory leak in irq setup of sclpconsole: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 89of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x800F5685: console_init (sclpconsole.c:235) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) ==42117== by 0x801CDC4B: property_set_bool (object.c:1337) ==42117== by 0x801CBD7F: object_property_set (object.c:819) [...] We dont need the indirection of an qemu irq to inject an slcp interrupt. Fixes a valgrind error and makes the code simpler. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
2014-03-17s390x/sclpconsole: Fix and simplify interrupt injectionChristian Borntraeger
valgrind complains about a memory leak in irq setup of sclpconsole: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 89 of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x800F5685: console_init (sclpconsole.c:235) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) ==42117== by 0x801CDC4B: property_set_bool (object.c:1337) ==42117== by 0x801CBD7F: object_property_set (object.c:819) [...] Turns out that we actually dont need the indirection, so trigger the sclp interrupt directly. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
2014-03-17s390x/cpu hotplug: Fix memory leakChristian Borntraeger
valgrind complains about the following: ==42117== 8 bytes in 1 blocks are definitely lost in loss record 88 of 833 ==42117== at 0x4031AFE: malloc (vg_replace_malloc.c:292) ==42117== by 0x8022F855: malloc_and_trace (vl.c:2715) ==42117== by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2) ==42117== by 0x800F696D: qemu_extend_irqs (irq.c:51) ==42117== by 0x800F6AF7: qemu_allocate_irqs (irq.c:68) ==42117== by 0x8029FA4B: irq_cpu_hotplug_init (sclpcpu.c:84) ==42117== by 0x80297C79: event_realize (event-facility.c:386) ==42117== by 0x80105071: device_set_realized (qdev.c:693) [...] Right it is. Don't drop the pointer of the irq. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Jason J. Herne <jjherne@us.ibm.com>
2014-03-17s390/ipl: Fix error path on BIOS loadingChristian Borntraeger
commit 18674b26788a9e47f1157170234e32ece2044367 (elf-loader: add more return codes) enabled the elf loader to return other errors than -1. Lets also handle that case for our "BIOS" on s390. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> CC: Alexey Kardashevskiy <aik@ozlabs.ru> CC: Alexander Graf <agraf@suse.de>
2014-03-17tcg-sparc: Convert to new ldst opcodesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Convert to new ldst helpersRichard Henderson
All of the helpers with the explicit big/little endian option require the return address as a parameter. Acquire this via a trampoline. Move the load of areg0 into the trampoline. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Tidy tcg_out_tlb_load interfaceRichard Henderson
Pass address registers explicitly, rather than as indicies of args[]. It's two argument registers either way. Use more TCGReg as appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Use TCGMemOp within qemu_ldst routinesRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Improve tcg_out_moviRichard Henderson
If bits 31:13 are zero, reduce the insn count by one. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Dont handle constant arguments to ext32 opsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Don't handle remainderRichard Henderson
The generic fallback is exactly what we implemented. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Use intptr_t as appropriateRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Tidy call+jump patternsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Fix tlb readRichard Henderson
We were computing the full address into %o0 and then not using it. Adjust some of the computation to rely less on having to pull immediate values into registers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Fix ld64 for 32-bit modeRichard Henderson
Since were not using an annulled branch, we need to put a nop in the delay slot. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17scripts/qemu-binfmt-conf.sh: Add AArch64 registrationPeter Maydell
Add the binfmt-misc magic needed to register QEMU for handling AArch64 ELF binaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-26-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell
Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée
This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée
Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
2014-03-17softfloat: export squash_input_denormal functionsAlex Bennée
I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-20-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell
Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org
2014-03-17exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell
The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FRINT*Peter Maydell
Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SRIPeter Maydell
Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée
These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell
Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell
Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell
Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
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