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2014-03-17tcg-sparc: Tidy call+jump patternsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Fix tlb readRichard Henderson
We were computing the full address into %o0 and then not using it. Adjust some of the computation to rely less on having to pull immediate values into registers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17tcg-sparc: Fix ld64 for 32-bit modeRichard Henderson
Since were not using an annulled branch, we need to put a nop in the delay slot. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-03-17scripts/qemu-binfmt-conf.sh: Add AArch64 registrationPeter Maydell
Add the binfmt-misc magic needed to register QEMU for handling AArch64 ELF binaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-26-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
This adds support for [UF]RSQRTE instructions. It utilises the existing NEON helpers with some changes. The changes include an explicit passing of fpstatus (so the correct one is used between arm32 and aarch64), denormilzation, more correct error handling and also proper scaling of the fraction going into the estimate. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell
Implement the FCVTXN operation, which does a narrowing fp precision conversion using the "round to odd" (von Neumann) mode. This can conveniently be implemented as "do operation using round to zero; then set the LSB of the mantissa to 1 if the Inexact flag was set". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée
This completes the set of integer narrowing saturating ops including: SQXTN, SQXTN2 SQXTUN, SQXTUN2 UQXTN, UQXTN2 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée
Move the handle_2misc_narrow() function up the file so that it can be called from disas_simd_scalar_two_reg_misc(). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
Implement URECPE and FRECPE instructions in both scalar and vector forms. The actual reciprocal estimate function is shared with the A32/T32 Neon code. However in A64 we aren't using the Neon "standard FPSCR value" so extra checks are necessary to handle non-squashed denormal inputs which can never happen for A32/T32. Calling conventions for the helpers are thus modified to pass the fpst directly; we mark the helpers as TCG_CALL_NO_RWG since we're changing the declarations anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org
2014-03-17softfloat: export squash_input_denormal functionsAlex Bennée
I need these available outside of softfloat for some of the reciprocal processing in aarch64 helper functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-20-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell
Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm categories; this completes the implementation of those two groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell
Implement the saturating left shift instructions SQSHL, SQSHLU and UQSHL for the scalar-shift-imm and shift-imm categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org
2014-03-17exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell
The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FRINT*Peter Maydell
Implement the FRINT* round-to-integral operations from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SRIPeter Maydell
Implement SRI (shift right and insert). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée
These are fairly simple exponent only estimation functions using helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell
Implement FCVTL, the only instruction in the 2-reg-misc group which widens from size to 2*size elements. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell
Implement the floating-point-to-integer conversion instructions FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc categories. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell
Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell
Implement the SADDLP, UADDLP, SADALP and UADALP instructions in the SIMD 2-reg misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Saturating and narrowing shift opsAlex Bennée
This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are saturating and narrowing shift right operations. These are used in things like libav. Note signed shifts can have an "unsigned" saturating narrow operation which will floor negative values. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-7-git-send-email-peter.maydell@linaro.org [PMM: Added the scalar encodings, style tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée
Implement the CLS, CLZ operations in the 2-reg-misc category. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-6-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée
Implement FSQRT in the two-reg-misc category. GCC uses this instruction form. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-5-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée
This adds the remaining [US]CVTF operations to the SIMD shift-immediate, scalar-shift-immediate, two-reg-misc and scalar-two-reg-misc groups of opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org [PMM: added scalar 2-misc and scalar-shift-imm encodings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée
rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-3-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell
Implement the PMULL instruction; this is the last unimplemented insn in the three-reg-diff group. Note that PMULL with size 3 is considered part of the AES part of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition in the v8 ARM ARM), so it isn't necessary to burn an extra feature bit on it, even though we're using more feature bits than a single "crypto extension present/not present" toggle. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
2014-03-17target-arm: Add ARM_CP_IO notation to PMCR reginfoPeter Maydell
Now that the PMCR writefn makes timer accesses, its reginfo needs the ARM_CP_IO flag, so that icount mode works correctly. (Fixes the bug accidentally introduced in commit 7c2cb42b). Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1394908291-16546-1-git-send-email-peter.maydell@linaro.org
2014-03-17virt: Set reset-cbar on CPUsPeter Maydell
Set the reset-cbar property on CPUs used by the virt board, if they have it. This isn't necessary for correct functioning under Linux (since the A9 isn't a valid CPU for the virt board), but it is the correct behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-5-git-send-email-peter.maydell@linaro.org
2014-03-17exynos4210: Set reset-cbar property of Cortex-A9 CPUsPeter Maydell
Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9 CPUs, so that Linux doesn't misrecognize them as a broken uniprocessor SoC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-4-git-send-email-peter.maydell@linaro.org
2014-03-17realview-pbx-a9: Set reset-cbar property for CPUsPeter Maydell
If the CPU is a Cortex-A9 then we should set its reset-cbar property so that the guest can read the correct PERIPHBASE/CBAR register value; newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) will otherwise assume the CPU is a buggy single core A9 SoC. The realview-pbx-a9 is the only one of the cluster of boards in realview.c which works with the Cortex-A9 (ie which gets an a9mpcore_priv device); make sure it also has reset-cbar set correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-3-git-send-email-peter.maydell@linaro.org
2014-03-17vexpress: Set reset-cbar property for CPUsPeter Maydell
Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) now assume that if the CPU is a Cortex-A9 and the reset value of the PERIPHBASE/CBAR register is zero then the CPU is a specific buggy single core A9 SoC, and will not try to start other cores. Since we now have a CPU property for the reset value of the CBAR, we can just fix the vexpress board model to correctly set CBAR so SMP works again. To avoid duplicate boilerplate code in both the A9 and A15 daughterboard init functions, we split out the CPU and private memory region init to its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-2-git-send-email-peter.maydell@linaro.org
2014-03-17Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-3' into stagingPeter Maydell
gtk: warp bugfixes. gtk: Allow to activate grab-on-hover from the command line # gpg: Signature made Mon 17 Mar 2014 13:35:35 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-gtk-3: gtk: Don't warp absolute pointer gtk: Fix mouse warping with gtk3 gtk: Allow to activate grab-on-hover from the command line Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17gtk: Don't warp absolute pointerCole Robinson
This matches the behavior of SDL, and makes the mouse usable when using -display gtk -vga qxl https://bugzilla.redhat.com/show_bug.cgi?id=1051724 Signed-off-by: Cole Robinson <crobinso@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-17gtk: Fix mouse warping with gtk3Cole Robinson
We were using the wrong coordinates, this fixes things to match the original gtk2 implementation. You can see this error in action by using -vga qxl, however even after this patch the mouse warps in small increments up and to the left, -7x and -3y pixels at a time, until the pointer is warped off the widget. I think it's a qxl bug, but the next patch covers it up. Signed-off-by: Cole Robinson <crobinso@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-17gtk: Allow to activate grab-on-hover from the command lineJan Kiszka
As long as we have no persistent GTK configuration, this allows to enable the useful grab-on-hover feature already when starting the VM. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> [ kraxel: fix warning with CONFIG_GTK=n ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-17linux-user: Implement capget, capsetPeter Maydell
Implement the capget and capset syscalls. This is useful because simple programs like 'ls' try to use it in AArch64, and otherwise we emit a lot of noise about it being unimplemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17Merge remote-tracking branch 'remotes/bonzini/fixes-for-2.0' into stagingPeter Maydell
* remotes/bonzini/fixes-for-2.0: vl.c: Output error on invalid machine type target-alpha: fix subl and s8subl indentation qemu-nbd: Fix coverity issues rules.mak: Fix per object libs extraction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17vl.c: Output error on invalid machine typeMiroslav Rezanina
Output error message using qemu's error_report() function when user provides the invalid machine type on the command line. This also saves time to find what issue is when you downgrade from one version of qemu to another that doesn't support required machine type yet (the version user downgraded to have to have this patch applied too, of course). Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com> [Replace printf with error_printf, suggested by Markus Armbruster. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-17target-alpha: fix subl and s8subl indentationPaolo Bonzini
Two missing braces, one close and one open, fabulously let the code compile. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-17qemu-nbd: Fix coverity issuesPaolo Bonzini
There are two issues in qemu-nbd: a missing return value check after calling accept(), and file descriptor leaks in nbd_client_thread. Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-17rules.mak: Fix per object libs extractionFam Zheng
Don't sort the extracted options, sort the objects. Reported-by: Christian Mahnke <cmahnke@googlemail.com> Signed-off-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-17Makefile: Fix "make clean"Fam Zheng
This fixes a dangerous bug: "make clean" after "make distclean" will delete every single file including those under .git, if you do in-tree build! Rationale: A first "make distclean" will unset $(DSOSUF), a following "make distclean" or "make clean" will find all the files and delete it. Fix it by explicitly typing the file extensions here, and combine multiple find invocations into one. Signed-off-by: Fam Zheng <famz@redhat.com> Message-id: 1395020122-4957-1-git-send-email-famz@redhat.com Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-17linux-user: Don't allow guest to block SIGSEGVPeter Maydell
Don't allow the linux-user guest to block SIGSEGV -- QEMU needs this signal to detect accesses to pages which it has marked read-only because it has cached translated code from them. We implement this by making the do_sigprocmask() wrapper suppress SIGSEGV when doing the host process signal mask manipulation; instead we store the current state of SIGSEGV in the TaskState struct. If we get a SIGSEGV for the guest when the guest has blocked the signal, we treat it as if the default SEGV handler was in place, as the kernel does for forced SIGSEGV delivery. This patch is based on an idea by Alex Barcelo, but rather than simply lying to the guest about the SIGSEGV state we track it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Alex Barcelo <abarcelo@ac.upc.edu> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17signal: added a wrapper for sigprocmask functionAlex Barcelo
Create a wrapper for signal mask changes initiated by the guest; (this includes syscalls and also the sigreturns from signal.c) this will give us a place to put code which prevents the guest from changing the handling of signals used by QEMU itself internally. The wrapper is called from all the guest-initiated sigprocmask, but is not called from internal qemu sigprocmask calls. Signed-off-by: Alex Barcelo <abarcelo@ac.upc.edu> [PMM: Added calls to wrapper for sigprocmask uses in signal.c when setting the signal mask on entry and exit from signal handlers, since these also are guest-provided signal masks.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17linux-user: Don't reserve space for commpage for AArch64Peter Maydell
AArch64 Linux, unlike AArch32, doesn't use a commpage. This means we should not be reserving room in the guest address space for one. Fixes LP:1287195. Reported-by: Amanieu d'Antras <amanieu@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17linux-user: implement F_[GS]ETOWN_EXAndreas Schwab
F_GETOWN is replaced by F_GETOWN_EX inside the glibc fcntl wrapper Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17linux-user: Don't return uninitialized value for atomic_barrier syscallPeter Maydell
QEMU's implementation of the m68k atomic_barrier syscall, like the kernel's, is just a no-op. However we still need to return a result code from it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-17linux-user/signal.c: Correct error path for AArch64 do_rt_sigreturnPeter Maydell
The error path in AArch64 do_rt_sigreturn() which fails before attempting lock_user_struct() was doing an unlock_user_struct() on an uninitialized variable. Initialize frame to NULL so we can use the same error-exit path in all cases (unlock of NULL is permitted and does nothing). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
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