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2014-03-05target-ppc: Add ISA 2.06 fcfid[u][s] InstructionsTom Musta
This patch adds the fcfids, fcfidu and fcfidus instructions which were introduced in Power ISA 2.06B. A common macro is provided to eliminate repetitious code, and the existing fcfid instruction is refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 Float to Integer InstructionsTom Musta
This patch adds the four floating point to integer conversion instructions introduced by Power ISA V2.06: - Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward Zero (fctiwuz) - Floating Convert to Integer Doubleword Unsigned (fctidu) - Floating Convert to Integer Doubleword Unsigned with Round Toward Zero (fctiduz) A common macro is developed to eliminate repetitious code. Existing instructions are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta
This patch adds a flag for the floating point conversion instructions introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 stbcx. and sthcx. InstructionsTom Musta
This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 lbarx, lharx InstructionsTom Musta
This patch adds the byte and halfword variants of the Load and Reserve instructions. Since there is much commonality among all forms of Load and Reserve, a macro is provided and the existing implementations of lwarx and ldarx are refactoried to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta
This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 divwe[o] InstructionsTom Musta
This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA 2.06 divweu[o] InstructionsTom Musta
This patch addes the Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta
This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta
This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta
This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add ISA2.06 bpermd InstructionTom Musta
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Scalar Non-Signalling ConversionsTom Musta
This patch adds the non-signalling scalar conversion instructions: - VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision Non-Signalling (xscvdpspn) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Scalar Round to Single PrecisionTom Musta
This patch adds the VSX Scalar Round to Single Precision (xsrsp) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Floating Merge Word InstructionsTom Musta
This patch adds the Floating Merge Even Word (fmrgew) and Floating Merge Odd Word (fmrgow) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Move To/From VSR InstructionsTom Musta
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz) and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These instructions are unusual in that they are considered a floating point instruction if the indexed VSR is in the first half of the array (0-31) but they are considered vector instructions if the indexed VSR is in the second half of the array (32-63). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorcTom Musta
This patchs adds the VSX Logical instructions that are new with ISA V2.07: - VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdspTom Musta
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword to Floating Point Format and Round to Single Precision (xscvuxdsp) and VSX Scalar Convert Signed Integer Douglbeword to Floating Point Format and Round to Single Precision (xscvsxdsp) instructions. The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP) is modified to support the rounding of the intermediate floating point result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-AddsTom Musta
This patch adds the Single Precision VSX Scalar Fused Multiply-Add instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp. The existing VSX_MADD() macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: add xsrsqrtespTom Musta
This patch adds the VSX Scalar Reciprocal Square Root Estimate Single Precision (xsrsqrtesp) instruction. The existing VSX_RSQRTE() macro is modified to support rounding of the intermediate double-precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xssqrtspTom Musta
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp) instruction. The existing VSX_SQRT() macro is modified to support rounding of the intermediate double-precision result to single-precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsrespTom Musta
This patch adds the VSX Scalar Reciprocal Estimate Single Precision (xsresp) instruction. The existing VSX_RE macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsdivspTom Musta
This patch adds the VSX Scalar Divide Single Precision (xsdivsp) instruction. The existing VSX_DIV macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsmulspTom Musta
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp) instruction. The existing VSX_MUL macro is modified to support rounding of the intermediate result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsaddsp and xssubspTom Musta
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and VSX Scalar Subtract Single-Precision (xssubsp) instructions. The existing VSX_ADD_SUB macro is modified to support the rounding of the (intermediate) result to single-precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add stxsiwx and stxsspxTom Musta
This patch adds two store scalar instructions: - Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Refactor stxsdxTom Musta
This patch refactors the stxsdx instruction. Reusable code is extracted into a macro which will be used in subsequent patches in this series. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspxTom Musta
This patch adds the scalar load instructions introduced in ISA V2.07: - Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax) - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx) - Load VSX Scalar Single-Precision Indexed (lxsspx) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Refactor lxsdxTom Musta
This patch refactors the lxsdx generator. Resuable code is isolated into a macro. The macro will be used in subsequent patches in this series to implement other scalar load instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta
This patch adds a flag to identify those VSX instructions that are new to Power ISA V2.07. The flag is added to the Power 8 processor initialization so that the P8 models understand how to decode and emulate instructions in this category. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Rounding InstructionsTom Musta
This patch adds the VSX Round to Floating Point Integer instructions: - xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 Integer Conversion InstructionsTom Musta
This patch adds the VSX Integer Conversion instructions defined by V2.06 of the PowerPC ISA: - xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws - xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws - xscvsxddp, xscvuxddp - xvcvsxddp, xscvsxwdp, xvcvuxddp, xvcvuxwdp - xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Floating Point to Floating Point Conversion InstructionsTom Musta
This patch adds the VSX instructions that convert between floating point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Vector Compare InstructionsTom Musta
This patch adds the VSX floating point compare vector instructions: - xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.] - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.] Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX xmax/xmin InstructionsTom Musta
This patch adds the VSX floating point maximum and minimum instructions: - xsmaxdp, xvmaxdp, xvmaxsp - xsmindp, xvmindp, xvminsp Because of the Power ISA definitions of maximum and minimum on various boundary cases, the standard softfloat comparison routines (e.g. float64_lt) do not work as well as one might think. Therefore specific routines for comparing 64 and 32 bit floating point numbers are implemented in the PowerPC helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX xscmp*dp InstructionsTom Musta
This patch adds the VSX scalar floating point compare ordered and unordered instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 Multiply Add InstructionsTom Musta
This patch adds the VSX floating point multiply/add instructions defined by V2.06 of the PowerPC ISA: - xsmaddadp, xvmaddadp, xvmaddasp - xsmaddmdp, xvmaddmdp, xvmaddmsp - xsmsubadp, xvmsubadp, xvmsubasp - xsmsubmdp, xvmsubmdp, xvmsubmsp - xsnmaddadp, xvnmaddadp, xvnmaddasp - xsnmaddmdp, xvnmaddmdp, xvnmaddmsp - xsnmsubadp, xvnmsubadp, xvnmsubasp - xsnmsubmdp, xvnmsubmdp, xvnmsubmsp Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xtsqrt InstructionsTom Musta
This patch adds the VSX floating point test for software square root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp, xvtsqrtdp, xvtsqrtsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xtdiv InstructionsTom Musta
This patch adds the VSX floating point test for software divide instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp, and xvtdivsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xrsqrte InstructionsTom Musta
This patch adds the VSX floating point reciprocal square root estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp, xvrsqrtedp, xvrsqrtesp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xsqrt InstructionsTom Musta
This patch adds the VSX floating point square root instructions defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xre InstructionsTom Musta
This patch adds the VSX floating point reciprocal estimate instructions defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xdiv InstructionsTom Musta
This patch adds the VSX floating point divide instructions defined by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xmul InstructionsTom Musta
This patch adds the VSX floating point multiply instructions defined by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xadd/xsub InstructionsTom Musta
This patch adds the floating point addition and subtraction instructions defined by V2.06 of the PowerPC ISA: xssubdp, xvsubdp and xvsubsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: General Support for VSX HelpersTom Musta
This patch adds general support that will be used by the VSX helper routines: - a union describing the various VSR subfields. - access routines to get and set VSRs - VSX decoders - a general routine to generate a handler that invokes a VSX helper. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add set_fprf Argument to fload_invalid_op_excp()Tom Musta
The fload_invalid_op_excp() function sets assorted invalid operation status bits. However, it also implicitly modifies the FPRF field of the PowerPC FPSCR. Many VSX instructions set invalid operation bits but do not alter FPRF. Thus the function is more generally useful if the setting of the FPRF field is made conditional via a parameter. All invocations of this routine in existing instructions are modified to pass 1 and thus retain their current behavior. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRLAlexey Kardashevskiy
The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL - no 32 S 152 00100 11000 CTRL yes - 32 S According to this chart, the hypervisor's CTRL (#152) does not support reading, the user-space's CTRL (UCTRL, #136) does not support writing. This replaces unsupported operations with the default SPR_NOACCESS hook. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05spapr_vscsi: Fix REPORT_LUNS handlingNathan Whitehorn
Intercept REPORT_LUNS commands addressed either to SRP LUN 0 or the well-known LUN for REPORT_LUNS commands. This is required to implement the SAM and SPC specifications. Since SRP implements only a single SCSI target port per connection, the SRP target is required to report all available LUNs in response to a REPORT_LUNS command addressed either to LUN 0 or the well-known LUN. Instead, QEMU was forwarding such requests to the first QEMU SCSI target, with the result that initiators that relied on this feature would only see LUNs on the first QEMU SCSI target. Behavior for REPORT_LUNS commands addressed to any other LUN is not specified by the standard and so is left unchanged. This preserves behavior under Linux and SLOF, which enumerate possible LUNs by hand and so address no commands either to LUN 0 or the well-known REPORT_LUNS LUN. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> [agraf: define constant as ULL for 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05spapr-pci: enable adding PHB via -deviceAlexey Kardashevskiy
Recent changes introduced cannot_instantiate_with_device_add_yet and removed capability of adding yet another PCI host bridge via command line for SPAPR platform (POWERPC64 server). This brings the capability back and puts SPAPR PHB into "bridge" category. This is not much use for emulated PHB but it is absolutely required for VFIO as we put an IOMMU group onto a separate PHB on SPAPR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
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