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2021-02-18hostmem: Don't report pmem attribute if unsupportedMichal Privoznik
When management applications (like Libvirt) want to check whether memory-backend-file.pmem is supported they can list object properties using 'qom-list-properties'. However, 'pmem' is declared always (and thus reported always) and only at runtime QEMU errors out if it was built without libpmem (and thus can not guarantee write persistence). This is suboptimal since we have ability to declare attributes at compile time. Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1915216 Message-Id: <dfcc5dc7e2efc0283bc38e3036da2c0323621cdb.1611647111.git.mprivozn@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-02-18device-crash-test: Remove problematic languageEduardo Habkost
Replace "whitelist" in the device-crash-test script with "rule list". I'm using "rule list" instead of "allow list" or "pass list" because the list is not used only for expected/allowed errors. It also contain rules specifying which errors shouldn't be ignored and/or should be fatal. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210202191207.4103973-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-02-18i386: Add the support for AMD EPYC 3rd generation processorsBabu Moger
Adds the support for AMD 3rd generation processors. The model display for the new processor will be EPYC-Milan. Adds the following new feature bits on top of the feature bits from the first and second generation EPYC models. pcid : Process context identifiers support ibrs : Indirect Branch Restricted Speculation ssbd : Speculative Store Bypass Disable erms : Enhanced REP MOVSB/STOSB support fsrm : Fast Short REP MOVSB support invpcid : Invalidate processor context ID pku : Protection keys support svme-addr-chk : SVM instructions address check for #GP handling Depends on the following kernel commits: 14c2bf81fcd2 ("KVM: SVM: Fix #GP handling for doubly-nested virtualization") 3b9c723ed7cf ("KVM: SVM: Add support for SVM instruction address check change") 4aa2691dcbd3 ("8ce1c461188799d863398dd2865d KVM: x86: Factor out x86 instruction emulation with decoding") 4407a797e941 ("KVM: SVM: Enable INVPCID feature on AMD") 9715092f8d7e ("KVM: X86: Move handling of INVPCID types to x86") 3f3393b3ce38 ("KVM: X86: Rename and move the function vmx_handle_memory_failure to x86.c") 830bd71f2c06 ("KVM: SVM: Remove set_cr_intercept, clr_cr_intercept and is_cr_intercept") 4c44e8d6c193 ("KVM: SVM: Add new intercept word in vmcb_control_area") c62e2e94b9d4 ("KVM: SVM: Modify 64 bit intercept field to two 32 bit vectors") 9780d51dc2af ("KVM: SVM: Modify intercept_exceptions to generic intercepts") 30abaa88382c ("KVM: SVM: Change intercept_dr to generic intercepts") 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts") c45ad7229d13 ("KVM: SVM: Introduce vmcb_(set_intercept/clr_intercept/_is_intercept)") a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field") fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code") 38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on AMD") 37486135d3a7 ("KVM: x86: Fix pkru save/restore when guest CR4.PKE=0, move it to x86.c") Signed-off-by: Babu Moger <babu.moger@amd.com> Message-Id: <161290460478.11352.8933244555799318236.stgit@bmoger-ubuntu> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-02-18Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' ↵Peter Maydell
into staging Initial commit for the Qualcomm Hexagon processor. # gpg: Signature made Thu 18 Feb 2021 16:26:52 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-hex-20210218: (35 commits) Hexagon build infrastructure Hexagon (tests/tcg/hexagon) TCG tests - floating point Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Hexagon (tests/tcg/hexagon) TCG tests - multiarch Hexagon (linux-user/hexagon) Linux user emulation Hexagon (target/hexagon) translation Hexagon (target/hexagon) TCG for floating point instructions Hexagon (target/hexagon) TCG for instructions with multiple definitions Hexagon (target/hexagon) TCG generation Hexagon (target/hexagon) instruction classes Hexagon (target/hexagon) macros Hexagon (target/hexagon) opcode data structures Hexagon (target/hexagon) generater phase 4 - decode tree Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Hexagon (target/hexagon) generator phase 2 - generate header files Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Hexagon (target/hexagon/imported) arch import Hexagon (target/hexagon/fma_emu.[ch]) utility functions Hexagon (target/hexagon/conv_emu.[ch]) utility functions Hexagon (target/hexagon/arch.[ch]) utility functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-18Hexagon build infrastructureTaylor Simpson
Add file to default-configs Add hexagon to meson.build Add hexagon to target/meson.build Add target/hexagon/meson.build Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" will pass. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-35-git-send-email-tsimpson@quicinc.com> [rth: Use top-level python variable] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - floating pointTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-34-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/miscTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-33-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (tests/tcg/hexagon) TCG tests - multiarchTaylor Simpson
Enable multiarch tests for Hexagon Modify tests/tcg/configure.sh Add reference files to tests/tcg/hexagon Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-32-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (linux-user/hexagon) Linux user emulationTaylor Simpson
Implementation of Linux user emulation for Hexagon Some common files modified in addition to new files in linux-user/hexagon Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-31-git-send-email-tsimpson@quicinc.com> [rth: Fix termbits.h on review by Laurent] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) translationTaylor Simpson
Read the instruction memory Create a packet data structure Generate TCG code for the start of the packet Invoke the generate function for each instruction Generate TCG code for the end of the packet Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-30-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) TCG for floating point instructionsTaylor Simpson
The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-29-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) TCG for instructions with multiple definitionsTaylor Simpson
Helpers won't work if there are multiple definitions, so we override these instructions using #define fGEN_TCG_<tag>. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-28-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) TCG generationTaylor Simpson
Include the generated files and set up the data structures Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) instruction classesTaylor Simpson
Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) macrosTaylor Simpson
macros to interface with the generator macros referenced in instruction semantics Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-25-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) opcode data structuresTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) generater phase 4 - decode treeTaylor Simpson
Python script that emits the decode tree in dectree_generated.h. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-23-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode treeTaylor Simpson
Run the C preprocessor across the instruction definition and encoding files to expand macros and prepare the iset.py file. The resulting fill contains python data structures used to build the decode tree. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-22-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) generator phase 2 - generate header filesTaylor Simpson
Python scripts generate the following files helper_protos_generated.h.inc For each instruction we create DEF_HELPER function prototype helper_funcs_generated.c.inc For each instruction we create the helper function definition tcg_funcs_generated.c.inc For each instruction we create TCG code to generate call to helper tcg_func_table_generated.c.inc Table of function pointers indexed by opcode shortcode_generated.h.inc Generate a table of instruction "shortcode" semantics opcodes_def_generated.h.inc Gives a list of all the opcodes op_attribs_generated.h.inc Lists all the attributes associated with each instruction op_regs_generated.h.inc Lists the register and immediate operands for each instruction printinsn_generated.h.inc Data for printing (disassembling) each instruction (format string + operands) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-21-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) generator phase 1 - C preprocessor for semanticsTaylor Simpson
Run the C preprocessor across the instruction definition files and macro definition file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-20-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon/imported) arch importTaylor Simpson
Imported from the Hexagon architecture library imported/macros.def The macro definitions specify instruction attributes that are applied to each instruction that references the macro. The generator will recursively apply attributes to each instruction that used the macro. imported/allidefs.def Top level instruction definition file imported/*.idef Instruction definition files These files are input to the first phase of the generator (gen_semantics.c) to create a python include file with the instruction semantics and attributes. The python include file is fed to the second phase to generate various header files. imported/encode*.def Instruction encoding bit patterns for every instruction Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-19-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon/fma_emu.[ch]) utility functionsTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-18-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon/conv_emu.[ch]) utility functionsTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-17-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon/arch.[ch]) utility functionsTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-16-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) instruction printingTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-15-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) instruction/packet decodeTaylor Simpson
Take the words from instruction memory and build a packet_t for TCG code generation The following operations are performed Convert the .new encoded offset to the register number of the producer Reorder the packet so .new producer is before consumer Apply constant extenders Separate subinsn's into two instructions Break compare-jumps into two instructions Create instructions for :endloop Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-14-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) instruction attributesTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-13-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) register fieldsTaylor Simpson
Declare bitfields within registers such as user status register (USR) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-12-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) instruction and packet typesTaylor Simpson
The insn_t and packet_t are the interface between instruction decoding and TCG code generation Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-11-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) architecture typesTaylor Simpson
Define types used in files imported from the Hexagon architecture library Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-10-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) GDB StubTaylor Simpson
GDB register read and write routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-9-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) scalar core helpersTaylor Simpson
The majority of helpers are generated. Define the helper functions needed then include the generated file Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-8-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) register namesTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-7-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (disas) disassemblerTaylor Simpson
Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-6-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) scalar core definitionTaylor Simpson
Add target state header, target definitions and initialization routines Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-5-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (include/elf.h) ELF machine definitionTaylor Simpson
Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-4-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon (target/hexagon) READMETaylor Simpson
Gives an introduction and overview to the Hexagon target Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-3-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18Hexagon Update MAINTAINERS fileTaylor Simpson
Add Taylor Simpson as the Hexagon target maintainer Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-2-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-18qemu/int128: Add int128_orRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201021045149.1582203-2-richard.henderson@linaro.org>
2021-02-18Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210218-pull-request' ↵Peter Maydell
into staging usb: two bugfixes. # gpg: Signature made Thu 18 Feb 2021 11:51:44 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20210218-pull-request: usb/pcap: set flag_setup usb-host: use correct altsetting in usb_host_ep_update Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-18Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-plugin-updates-180221-1' into staging Plugin updates: - expose vdev name in PCI memory registration - new hwprofile plugin - bunch of style cleanups to contrib/plugins - fix call signature of inline instrumentation - re-factor the io_recompile code to push specialisation into hooks - add some acceptance tests for the plugins - clean-up and remove CF_NOCACHE handling from TCG - fix instrumentation of cpu_io_recompile sections - expand tests to check inline and cb count the same # gpg: Signature made Thu 18 Feb 2021 08:24:57 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-plugin-updates-180221-1: (23 commits) tests/acceptance: add a memory callback check tests/plugin: allow memory plugin to do both inline and callbacks tests/acceptance: add a new tests to detect counting errors accel/tcg: allow plugin instrumentation to be disable via cflags accel/tcg: remove CF_NOCACHE and special cases accel/tcg: re-factor non-RAM execution code accel/tcg: cache single instruction TB on pending replay exception accel/tcg: actually cache our partial icount TB tests/acceptance: add a new set of tests to exercise plugins tests/plugin: expand insn test to detect duplicate instructions target/sh4: Create superh_io_recompile_replay_branch target/mips: Create mips_io_recompile_replay_branch accel/tcg: Create io_recompile_replay_branch hook exec: Move TranslationBlock typedef to qemu/typedefs.h accel/tcg/plugin-gen: fix the call signature for inline callbacks contrib: Open brace '{' following struct go on the same line contrib: space required after that ',' contrib: Add spaces around operator contrib: Fix some code style problems, ERROR: "foo * bar" should be "foo *bar" contrib: Don't use '#' flag of printf format ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-18tests/acceptance: add a memory callback checkAlex Bennée
This test makes sure that the inline and callback based memory checks count the same number of accesses. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-24-alex.bennee@linaro.org>
2021-02-18tests/plugin: allow memory plugin to do both inline and callbacksAlex Bennée
This is going to be useful for acceptance tests that check both types are being called the same number of times, especially when icount is enabled. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-23-alex.bennee@linaro.org>
2021-02-18tests/acceptance: add a new tests to detect counting errorsAlex Bennée
The insn plugin has a simple heuristic to detect if an instruction is detected running twice in a row. Check the plugin log after the run and pass accordingly. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-22-alex.bennee@linaro.org>
2021-02-18accel/tcg: allow plugin instrumentation to be disable via cflagsAlex Bennée
When icount is enabled and we recompile an MMIO access we end up double counting the instruction execution. To avoid this we introduce the CF_MEMI cflag which only allows memory instrumentation for the next TB (which won't yet have been counted). As this is part of the hashed compile flags we will only execute the generated TB while coming out of a cpu_io_recompile. While we are at it delete the old TODO. We might as well keep the translation handy as it's likely you will repeatedly hit it on each MMIO access. Reported-by: Aaron Lindsay <aaron@os.amperecomputing.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-21-alex.bennee@linaro.org>
2021-02-18accel/tcg: remove CF_NOCACHE and special casesAlex Bennée
Now we no longer generate CF_NOCACHE blocks we can remove a bunch of the special case handling for them. While we are at it we can remove the unused tb->orig_tb field and save a few bytes on the TB structure. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-20-alex.bennee@linaro.org>
2021-02-18accel/tcg: re-factor non-RAM execution codeAlex Bennée
There is no real need to use CF_NOCACHE here. As long as the TB isn't linked to other TBs or included in the QHT or jump cache then it will only get executed once. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-19-alex.bennee@linaro.org>
2021-02-18accel/tcg: cache single instruction TB on pending replay exceptionAlex Bennée
Again there is no reason to jump through the nocache hoops to execute a single instruction block. We do have to add an additional wrinkle to the cpu_handle_interrupt case to ensure we let through a TB where we have specifically disabled icount for the block. As the last user of cpu_exec_nocache we can now remove the function. Further clean-up will follow in subsequent patches. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-18-alex.bennee@linaro.org>
2021-02-18accel/tcg: actually cache our partial icount TBAlex Bennée
When we exit a block under icount with instructions left to execute we might need a shorter than normal block to take us to the next deterministic event. Instead of creating a throwaway block on demand we use the existing compile flags mechanism to ensure we fetch (or compile and fetch) a block with exactly the number of instructions we need. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210213130325.14781-17-alex.bennee@linaro.org>
2021-02-18tests/acceptance: add a new set of tests to exercise pluginsAlex Bennée
This is just a simple test to count the instructions executed by a kernel. However a later test will detect a failure condition when icount is enabled. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210213130325.14781-16-alex.bennee@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-08 17:54:09 +0000