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2013-03-08target-ppc: Convert CPU definitionsAndreas Färber
Turn the array of model definitions into a set of self-registering QOM types with their own class_init. Unique identifiers are obtained from the combination of PVR, SVR and family identifiers; this requires all alias #defines to be removed from the list. Possibly there are some more left after this commit that are not currently being compiled. Prepares for introducing abstract intermediate CPU types for families. Keep the right-aligned macro line breaks within 78 chars to aid three-way merges. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Get model name from type nameAndreas Färber
We are about to drop the redundant name field along with ppc_def_t. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract POWER7 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 970 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 405GPe aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC8240 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC5200/MPC5200B aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC52xx aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx_HiP{3, 4} aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx aliases to *_HiP4Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC8247/MPC8248/MPC8270-80 aliasesAndreas Färber
This depends on the fix for "G2leGP3" PVR. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC82xx aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e200 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e300 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC83xx aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract e500v1/e500v2 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC85xx aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 604e aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 601/601v aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 603r aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 603e aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 740/750 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 750 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7x5 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7400 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7410 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7448 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 7450 aliasAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x1 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x5 as aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 74x7[A] aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Turn "ppc32" and "ppc64" CPUs into aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 440 aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract 40x aliasesAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MGT823/MPC8xx as aliasesAndreas Färber
They used different PVRs but were defined to MPC8xx. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract MPC5xx aliasesAndreas Färber
Their PVR differed but was defined to MPC5xx. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Make -cpu "ppc" an alias to "ppc32"Andreas Färber
Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64. If we ever want to change it, we can more easily do so now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Extract aliases from definitions listAndreas Färber
Move definitions that were 100% identical except for the name into a list of aliases so that we don't register duplicate CPU types. Drop the accompanying comments since they don't really add value. We need to support recursive lookup due to code names referencing a generic name referencing a specific model revision. List aliases separately for -cpu ?. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Inline comma into POWERPC_DEF_SVR() macroAndreas Färber
To repurpose the POWERPC_DEF_SVR() macro outside of an array, move the comma into the macro. No functional change. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Drop nested TARGET_PPC64 guard for POWER7Andreas Färber
It is within a large TARGET_PPC64 section from 970 to 620, so an #endif /* TARGET_PPC64 */ is confusing. Clean this up. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Update error handling in ppc_cpu_realize()Andreas Färber
Commit fe828a4d4b7a5617cda7b24e95e327bfb71d790e added a new fatal error message while QOM realize'ification was in flight. Convert it to return an Error instead of exit()ing. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix "G2leGP3" PVRAndreas Färber
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the "G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR. Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to "G2leGP3". Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08target-ppc: Fix CPU_POWERPC_MPC8547EAndreas Färber
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21. Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show. Fixing this nontheless helps with QOM'ifying CPU aliases. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-08pseries: Add cleanup hook for PAPR virtual LAN deviceDavid Gibson
Currently the spapr-vlan device does not supply a cleanup call for its NetClientInfo structure. With current qemu versions, that leads to a SEGV on exit, when net_cleanup() attempts to call the cleanup handlers on all net clients. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-07hw/nand.c: correct the sense of the BUSY/READY status bitKuo-Jung Su
The BIT6 of Status Register(SR): SR[6] behaves the same as R/B# pin SR[6] = 0 indicates the device is busy; SR[6] = 1 means the device is ready Some NAND flash controller (i.e. ftnandc021) relies on the SR[6] to determine if the NAND flash erase/program is success or error timeout. P.S: The exmaple NAND flash datasheet could be found at following link: http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf Signed-off-by: Kuo-Jung Su <dantesu@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-03-05Merge branch 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-armAurelien Jarno
* 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm: MAINTAINERS: add entry for ARM KVM guest cores configure: Enable KVM on ARM hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC target-arm: Use MemoryListener to identify GIC base address for KVM hw/arm_gic: Convert ARM GIC classes to use init/realize hw/arm_gic: Add presave/postload hooks ARM KVM: save and load VFP registers from kernel ARM: KVM: Add support for KVM on ARM architecture target-arm: Drop CPUARMState* argument from bank_number() linux-headers: resync from mainline to add ARM KVM headers oslib-posix: Align to permit transparent hugepages on ARM Linux target-arm: Don't decode RFE or SRS on M profile cores target-arm: Factor out handling of SRS instruction
2013-03-05mipsn32-linux-user: Configure the architecture properlyRichard Henderson
N32 is a 64-bit cpu with a 32-bit address space. We have existing cpp defines for this situation, but weren't using them. This does mean that the linux-user/mipsn32 directory must be merged with the linux-user/mips64 directory, and differences must be resolved via ifdefs. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05mips64-linux-user: Enable 64-bit address mode and fpuRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05mips-linux-user: Fix n32 and n64 syscallsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-05mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-10 21:17:21 +0000