aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2014-03-10linux-user: set minimum kernel version to 2.6.32Riku Voipio
Popular glibc based distributions[1] require minimum 2.6.32 as kernel version. For some targets 2.6.18 would be enough, but dropping so low would mean some suboptimal system calls could get used. Set the minimum kernel advertized to 2.6.32 for all architectures but aarch64 to ensure working qemu linux-user in case host kernel is older. [1] https://bugs.launchpad.net/ubuntu/+source/eglibc/+bug/921078 Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-03linux-user: correct handling of break exception for MIPSPetar Jovanovic
Exception with break instruction has not been correctly propagated as SIGTRAP. This resolves crash issues with examples that use break instruction on MIPS. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-03-03linux-user: translate signal number on return from sigtimedwaitPetar Jovanovic
On success, sigtimedwait() returns a signal number that needs to be translated from a host value to a target value. This change also fixes issues with sigwait (that is implemented using sigtimedwait()). Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-03linux-user: Implement sendmmsg syscallAlexander Graf
Glibc when built for newer kernels assumes that the sendmmsg syscall is available. Without it, dns resolution simply fails to work. Wrap the syscall with existing infrastructure so that we don't have a host dependency on sendmmsg. To avoid locking the same area of guest memory twice (which will break if DEBUG_REMAP is defined) we pull the lock/unlock part of do_sendrecvmsg() out into its own function so the actual implementation can be shared. Signed-off-by: Alexander Graf <agraf@suse.de> [PMM: add recvmmsg support; handle errors (which also implies support for non-blocking operations); cap the vector length as the kernel implementation does; don't lock guest memory twice; support MSG_WAITFORONE flag] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-03linux-user: Fix getresuid, getresgid if !USE_UID16Peter Maydell
The size of the UID/GID types depends on whether USE_UID16 is defined. Define a new put_user_id() which writes a uid/gid type to guest memory. This fixes getresuid and getresgid, which were always storing 16 bits even if the uid type was 32 bits. Reported-by: Michael Matz <matz@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-03linux-user: Don't use UID16 on AArch64Andreas Schwab
The AArch64 kernel defines its __kernel_uid_t type as 32 bits, unlike 32 bit ARM, so don't enable our 16-bit UID wrapper handling. Signed-off-by: Andreas Schwab <schwab@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-03linux-user: AArch64: Implement SA_RESTORER for signal handlersMichael Matz
Implement support for signal handlers with the SA_RESTORER flag set. Signed-off-by: Michael Matz <matz@suse.de> [PMM: minor tweaks to make patch apply to current master] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-03linux-user/signal.c: Fix AArch64 big-endian FP register restorePeter Maydell
Fix the loop restoring the FP registers from the signal frame to match the one used when setting up the signal frame, so that it handles TARGET_WORDS_BIGENDIAN being set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-28modules: Fix building with --enable-modulesFam Zheng
Compiling util/modules.c with modules enabled fails now. Fix it by including qemu-common.h before #ifdef testing in module.c. Signed-off-by: Fam Zheng <famz@redhat.com> Message-id: 1393453893-12125-1-git-send-email-famz@redhat.com Reviewed-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-27Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell
* remotes/kvm/uq/master: KVM: Use return value for error print Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-27Merge remote-tracking branch ↵Peter Maydell
'remotes/awilliam/tags/vfio-pci-for-qemu-20140226.0' into staging Updates include: - Coverify fixes for vfio & pci-assign (Markus) - VFIO blacklisting support for known brokwn PCI option ROMs (Bandan) # gpg: Signature made Wed 26 Feb 2014 18:15:28 GMT using RSA key ID 3BB08B22 # gpg: Can't check signature: public key not found * remotes/awilliam/tags/vfio-pci-for-qemu-20140226.0: vfio: blacklist loading of unstable roms qdev-monitor: set DeviceState opts before calling realize pci-assign: Fix potential read beyond buffer on -EBUSY vfio: Fix overrun after readlink() fills buffer completely Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140226' into staging target-arm queue: * fixes for various Coverity-spotted bugs * support new KVM device control API for VGIC * support KVM VGIC save/restore/migration * more AArch64 system mode foundations * support ARMv8 CRC instructions for A32/T32 * PL330 minor fixes and cleanup # gpg: Signature made Wed 26 Feb 2014 17:51:32 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140226: (45 commits) dma/pl330: implement dmaadnh instruction dma/pl330: Fix buffer depth dma/pl330: Add event debugging printfs dma/pl330: Rename parent_obj dma/pl330: printf format type sweep. dma/pl330: Fix misleading type dma/pl330: Delete overly verbose debug printf target-arm: Add support for AArch32 ARMv8 CRC32 instructions include/qemu/crc32c.h: Rename include guards to match filename target-arm: Add utility function for checking AA32/64 state of an EL target-arm: Implement AArch64 view of CPACR target-arm: A64: Implement MSR (immediate) instructions target-arm: Store AIF bits in env->pstate for AArch32 target-arm: A64: Implement WFI target-arm: Get MMU index information correct for A64 code target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI target-arm: Implement AArch64 dummy breakpoint and watchpoint registers target-arm: Implement AArch64 ID and feature registers target-arm: Implement AArch64 generic timers target-arm: Implement AArch64 MPIDR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140225' ↵Peter Maydell
into staging migration/next for 20140225 # gpg: Signature made Tue 25 Feb 2014 14:04:31 GMT using RSA key ID 5872D723 # gpg: Can't check signature: public key not found * remotes/juanquintela/tags/migration/20140225: rdma: rename 'x-rdma' => 'rdma' Fix two XBZRLE corruption issues Fix vmstate_info_int32_le comparison/assign qemu_file: use fwrite() correctly Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell
staging Net patches # gpg: Signature made Tue 25 Feb 2014 13:32:33 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/net-pull-request: virtio-net: use qemu_get_queue() where possible vhost_net: use offload API instead of bypassing it net: remove implicit peer from offload API net: Disable netmap backend when not supported net: add offloading support to netmap backend net: make tap offloading callbacks static net: virtio-net and vmxnet3 use offloading API net: TAP uses NetClientInfo offloading callbacks net: extend NetClientInfo for offloading net: change vnet-hdr TAP prototypes opencores_eth: flush queue whenever can_receive can go from false to true Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26Merge remote-tracking branch 'remotes/kraxel/tags/pull-audio-3' into stagingPeter Maydell
hda-audio: qom cleanups # gpg: Signature made Mon 24 Feb 2014 12:19:48 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-audio-3: hda-audio: qom cleanups Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26vfio: blacklist loading of unstable romsBandan Das
Certain cards such as the Broadcom BCM57810 have rom quirks that exhibit unstable system behavior duing device assignment. In the particular case of 57810, rom execution hangs and if a FLR follows, the device becomes inoperable until a power cycle. This change blacklists loading of rom for such cards unless the user specifies a romfile or rombar=1 on the cmd line Signed-off-by: Bandan Das <bsd@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-02-26qdev-monitor: set DeviceState opts before calling realizeBandan Das
Setting opts before the realize property is set allows the following patch to make decisions based on whether the user specified "rombar". This also avoids having to create a new tristate property especially for this purpose Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Bandan Das <bsd@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-02-26pci-assign: Fix potential read beyond buffer on -EBUSYMarkus Armbruster
readlink() doesn't write a terminating null byte. assign_failed_examine() passes the unterminated string to strrchr(). Oops. Terminate it. Spotted by Coverity. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-02-26vfio: Fix overrun after readlink() fills buffer completelyMarkus Armbruster
readlink() returns the number of bytes written to the buffer, and it doesn't write a terminating null byte. vfio_init() writes it itself. Overruns the buffer when readlink() filled it completely. Fix by treating readlink() filling the buffer completely as error, like we do in pci-assign.c's assign_failed_examine(). Spotted by Coverity. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-02-26dma/pl330: implement dmaadnh instructionPeter Crosthwaite
Implement the missing DMAADNH instruction. This is a minor variant of the DMAADDH instruction, so factor out to a common implementation for both (dmaadxh). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 73ab13532a7cae53441da89b46c279b5f50785e3.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: Fix buffer depthPeter Crosthwaite
This is the product of the data-width and the depth arguments, I.e the depth of the FIFO is in terms of data entries and not bytes (which is what the original implementation was suggesting). Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: c34de31031511538ccdb3164b48ee8a6a973ebd4.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: Add event debugging printfsPeter Crosthwaite
These are helpful to anyone trying to debug event sequencing. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: e82a0ad804db3de4f46839e55a9d287735ef870d.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: Rename parent_objPeter Crosthwaite
As per current QOM conventions. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: abb137347ea1ee9c31487b544f3d5435fb17f6a4.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: printf format type sweep.Peter Crosthwaite
Use PRI formats as appropriate rather than raw %x and %d. This fixes debug printfery on some host platforms. Fix types of debug only variables as appropriate. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: dbb5f5fd048b2d4a3cb5c6357577d11211a7a585.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: Fix misleading typePeter Crosthwaite
This type really should just be a regular int as no usages rely on it's 32 bitness (it's only meaningful as a bit position and not a bit mask). This also fixes a printf which uses the variable with a regular %d. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 2a99d31f377aee371476d9da8fd0d1b7efa30f63.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26dma/pl330: Delete overly verbose debug printfPeter Crosthwaite
When using event synchronisation, this particular debug printf floods. Just delete it. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: dd94d19493f97c47497b9d8caf74ca43e70d58fd.1393372019.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8 and add a CPU feature flag to enable these instructions. The CRC32-C implementation used is the built-in qemu implementation and The CRC-32 implementation is from zlib. This requires adding zlib to LIBS to ensure it is linked for the linux-user binary. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26include/qemu/crc32c.h: Rename include guards to match filenameWill Newton
Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1393411566-24104-2-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: Add utility function for checking AA32/64 state of an ELPeter Maydell
There are various situations where we need to behave differently depending on whether a given exception level is in AArch64 or AArch32 state. The state of the current exception level is stored in env->aarch64, but there's no equivalent guest-visible architected state bits for the status of the exception levels "above" the current one which may still affect execution. At the moment we only support EL1 (ie no EL2 or EL3) and insist that AArch64 capable CPUs run with EL1 in AArch64 state, but these may change in the future, so abstract out the "what state is this?" check into a utility function which can be enhanced later if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 view of CPACRPeter Maydell
Implement the AArch64 view of the CPACR. The AArch64 CPACR is defined to have a lot of RES0 bits, but since the architecture defines that RES0 bits may be implemented as reads-as-written and we know that a v8 CPU will have no registered coprocessors for cp0..cp13 we can safely implement the whole register this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell
Implement the MSR (immediate) instructions, which can update the PSTATE SP and DAIF fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell
To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: A64: Implement WFIPeter Maydell
Implement the WFI instruction for A64; this just involves wiring up the instruction, and adding a gen_a64_set_pc_im() which was accidentally omitted from the A64 decoder top loop. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Get MMU index information correct for A64 codePeter Maydell
Emit the correct MMU index information for loads and stores from A64 code, rather than hardwiring it to "always kernel mode", by storing the exception level in the TB flags, and make cpu_mmu_index() return the right answer when the CPU is in AArch64 mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 OSLAR_EL1 sysreg as WIPeter Maydell
Define a dummy version of the AArch64 OSLAR_EL1 system register which just ignores writes. Linux will always write to this (it is the OS lock used for debugging), but we don't support debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell
In AArch64 the breakpoint and watchpoint registers are mandatory, so the kernel always accesses them on bootup. Implement dummy versions, which read as written but have no actual effect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 ID and feature registersPeter Maydell
Implement the AArch64-specific ID and feature registers. Although many of these are currently not used by the architecture (and so always zero for all implementations), we define the full set of fields in the ARMCPU struct for symmetry. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 generic timersPeter Maydell
Implement the AArch64 view of the generic timer system registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: Implement AArch64 MPIDRPeter Maydell
Implement the AArch64 MPIDR system register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 TTBR*Peter Maydell
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 VBAR_EL1Peter Maydell
Implement the A64 view of the VBAR system register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 TCR_EL1Peter Maydell
Implement the AArch64 TCR_EL1, which is the 64 bit view of the AArch32 TTBCR. (The uses of the bits in the register are completely different, but in any given situation the CPU will always interpret them one way or the other. In fact for QEMU EL1 is always 64 bit, but we share the state field because this is the correct mapping to permit a future implementation of EL2.) We also make the AArch64 view the 'master' as far as migration and reset is concerned. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 SCTLR_EL1Peter Maydell
Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 memory attribute registersPeter Maydell
Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 dummy MDSCR_EL1Peter Maydell
We don't support letting the guest do debug, but Linux prods the monitor debug system control register anyway, so implement a dummy RAZ/WI version. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 TLB invalidate opsPeter Maydell
Implement the AArch64 TLB invalidate operations. This is the full set of TLBI ops defined for a CPU which doesn't implement EL2 or EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell
Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 MIDR_EL1Peter Maydell
Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell
Implement the CurrentEL sysreg. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementation in favour of using the CPU-specified reset value, and implement the system-mode-required semantics of restricting its EL0 accessibility if SCTLR.UCT is not set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-22 18:28:33 +0000