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2008-09-11uhci: Change default transaction lifetime to 32 frames (Max Krasnyansky)aliguori
Transaction lifetime was originally set to 10 frames. That was an arbitrary number I picked without much thinking :). I'm changing that to 32 frames because things like interrupt transfers and such are scheduled at that rate. It seems like 1/32 is accepted as lowest supported rate. OHCI, for example, defines exactly 32 interrupt heads. While testing USB webcam under XP I noticed that interrupt transactions were being canceled and then resubmitted on a regular basis, which works but is a waste of CPU cycles. This change fixes that. All other devices I have are not affected. Signed-off-by: Max Krasnyansky <maxk@kernel.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5199 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11Enable gcc flag -Wendif-labelsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5198 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11Only build compatfd when using AIO and make sure to always init AIOaliguori
OpenBSD doesn't use AIO so don't try to build compatfd when not using AIO. Also make sure to call qemu_aio_init() from bdrv_init. Everything that uses bdrv calls bdrv_init so it makes sense to init aio from there instead of in every single tool. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5197 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11Write zeros to high bits of y, based on patch by Vince Weaverblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11Make sure to read siginfo from signalfdaliguori
Otherwise, we'll idle at 100% cpu. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5195 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-11Fix the build on non-Linux systemsaliguori
It turns out, we're never reading from the signalfd() which is causing it to remain readable forever. I'll fix this up but I thought I'd commit this fix in the interim. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5194 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Partially convert float128 conversion ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic float32 ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Add missing files from previous commit.aliguori
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5188 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Use signalfd() to work around signal/select racealiguori
This patch introduces signalfd() to work around the signal/select race in checking for AIO completions. For platforms that don't support signalfd(), we emulate it with threads. There was a long discussion about this approach. I don't believe there are any fundamental problems with this approach and I believe eliminating the use of signals is a good thing. I've tested Windows and Linux using Windows and Linux guests. I've also checked for disk IO performance regressions. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5187 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10qemu-nbd: remove useless parameter from nbd_negotiate() (Laurent Vivier)aliguori
This patch removes "BlockDriverState *bs" from nbd_negotiate() because it is not used. Signed-off-by: Laurent Vivier <Laurent.Vivier@bull.fr> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5186 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Add missing "static"blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5184 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Add gitignore filealiguori
While QEMU officially uses SVN, there are a number of unofficial git repositories that many developers use. Adding a .gitignore (derived from the svn:ignore) will make their lives a lot easier. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5183 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Fix up pxe boot (Glauber Costa)aliguori
As discussed in http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html, current pxe boot is broken for some use cases. The problem goes away if we reduce the number of allowed bits in the address space to 32 (which has the side effect of reducing guest max mem size to 4Gb). After digging for a while, it turns out that it happens because pxelinux tries to access address 0x10009e9a6, which does not fit a 32-bit address. A closer look, however, reveals this access is totally valid: It's just 0x9e9a6 with an add carry. To avoid this, this patch casts the address passed to the POPL macro to a 32-bit value. This is also done, although just theorectically, for PUSHL too. Signed-off-by: Glauber Costa <glommer@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Reported-by: Chris Lalancette <clalance@redhat.com> CC: Eduardo Habkost <ehabkost@redhat.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5182 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07alpha: only print debug information to the log fileaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5181 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07TCG: Use x86-64 zero extension instructions.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5180 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07Implement TCG sign extension ops for x86-64.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5179 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-07Fix libvdeplug link test.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5178 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Fix a typo in fpsub32blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Convert most env fields to TCG registersblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Silence gcc warning about constant overflowblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Enable gcc flag -Wundefblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5174 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Fix most warnings that would be caused by gcc flag -Wundefblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5173 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-06Some little fixes on QEMUaurel32
- some vectors can be declared as "const" - test on CONFIG_VNC_TLS is done for two times while just one is enough. (Carlo Bramini) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5172 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05fix alpha cmovxx instructionaurel32
The CMOV instruction is defined by the alpha manual as: CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format Operation: IF TEST(Rav, Condition_based_on_Opcode) THEN Rc ← Rbv The current qemu behavior inverses Ra and Rb. This is fixed by this patch. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05CRIS: Mask off the cache selection bit after MMU translations.edgar_igl
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5170 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05Revert "TCG: enable debug"aurel32
This reverts commit 5166, commited by error. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5169 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05ppc: Convert op_subf to TCGaurel32
Replace op_subf with tcg_gen_sub_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05ppc: Convert op_add, op_addi to TCGaurel32
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05TCG: enable debugaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5166 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05TCG fixes for target-crisaurel32
This patch fixes TCG errors reported on the CRIS target when TCG_DEBUG is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Edgar E. Iglesias <edgar@axis.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5165 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05TCG fixes for target-mipsaurel32
This patch fixes TCG errors reported on the MIPS target when TCG_DEBUG is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Thiemo Seufer <ths@networkno.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5164 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05Fix swapped mvz/mvs instructions.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5163 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: replace op_set_FT0 with tcg_gen_movi_i64aurel32
Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: add target-alpha/helper.h (missing from commit r5150)aurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert nip moves to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: remove unused codeaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert CRF moves to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: fix fpr TCG registers creationaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert FPR moves to TCGaurel32
Replace op_{load,store}_fpr with tcg_gen_mov_i64. Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2]. This obsoletes op_template.h for REG > 7. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert Altivec register moves to TCGaurel32
Replace op_{load,store}_avr with helpers gen_{load,store}_avr. Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and cpu_AVR{h,l}[0..2]. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: cleanup register typesaurel32
- use target_ulong for gpr and dyngen registers - remove ppc_gpr_t type - define 64-bit dyngen registers for GPE register on 32-bit targets Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04ppc: Convert GPR moves to TCGaurel32
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl. Introduce TCG variables cpu_gpr[0..31]. For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64. Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: convert a few more instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: directly access ir registersaurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04convert of few alpha insn to TCGaurel32
(based on a patch from Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
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