aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2020-11-04s390-bios: Skip writing iplb location to low core for ccw iplJason J. Herne
2020-11-03Update version for v5.2.0-rc0 releasev5.2.0-rc0Peter Maydell
2020-11-03Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201...Peter Maydell
2020-11-03Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
2020-11-03block/vvfat: Fix bad printf format specifiersAlexChen
2020-11-03iotests: Use Python 3 style super()Kevin Wolf
2020-11-03iotests: Disable unsubscriptable-object in pylintKevin Wolf
2020-11-03iotests.py: Fix type check errors in wait_migration()Kevin Wolf
2020-11-03qemu-img convert: Free @sn_opts in all error casesTuguoyi
2020-11-03qmp: fix aio_poll() assertion failure on WindowsVolker Rümelin
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng
2020-11-03hw/misc: Add Microchip PolarFire SoC SYSREG module supportBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng
2020-11-03hw/misc: Add Microchip PolarFire SoC IOSCB module supportBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng
2020-11-03hw/misc: Add Microchip PolarFire SoC DDR Memory Controller supportBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng
2020-11-03target/riscv: Add sifive_plic vmstateYifei Jiang
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel
2020-11-03Merge remote-tracking branch 'remotes/berrange-gitlab/tags/sock-next-pull-req...Peter Maydell
2020-11-03sockets: Make abstract UnixSocketAddress depend on CONFIG_LINUXMarkus Armbruster
2020-11-03sockets: Bypass "replace empty @path" for abstract unix socketsMarkus Armbruster
2020-11-03char-socket: Fix qemu_chr_socket_address() for abstract socketsMarkus Armbruster
2020-11-03sockets: Fix socket_sockaddr_to_address_unix() for abstract socketsMarkus Armbruster
2020-11-03sockets: Fix default of UnixSocketAddress member @tightMarkus Armbruster
2020-11-03test-util-sockets: Test the complete abstract socket matrixMarkus Armbruster
2020-11-03test-util-sockets: Synchronize properly, don't sleep(1)Markus Armbruster
2020-11-03test-util-sockets: Factor out test_socket_unix_abstract_one()Markus Armbruster
2020-11-03test-util-sockets: Clean up SocketAddress constructionMarkus Armbruster
2020-11-03test-util-sockets: Correct to set has_abstract, has_tightMarkus Armbruster
2020-11-03test-util-sockets: Plug file descriptor leakMarkus Armbruster
2020-11-03Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag'...Peter Maydell
2020-11-03Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201102'...Peter Maydell
2020-11-02qga: add ssh-get-authorized-keysMarc-André Lureau
2020-11-02meson: minor simplificationMarc-André Lureau
2020-11-02qga: add *reset argument to ssh-add-authorized-keysMichael Roth
2020-11-02qga: add ssh-{add,remove}-authorized-keysMarc-André Lureau
2020-11-02glib-compat: add g_unix_get_passwd_entry_qemu()Marc-André Lureau
2020-11-02Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20201102a'...Peter Maydell
2020-11-02tests/acceptance: Add virtiofs_submounts.pyMax Reitz
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-19 05:20:12 +0000