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2023-09-11Merge tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qem...Stefan Hajnoczi
2023-09-11Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingStefan Hajnoczi
2023-09-11Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydel...Stefan Hajnoczi
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu
2023-09-11target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changesLeon Schuermann
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki
2023-09-11target/riscv: Use accelerated helper for AES64KS1IArd Biesheuvel
2023-09-11linux-user/riscv: Add new extensions to hwprobeRobbin Ehn
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza
2023-09-11hw/riscv/virt.c: fix non-KVM --enable-debug buildDaniel Henrique Barboza
2023-09-11riscv: zicond: make non-experimentalVineet Gupta
2023-09-11target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0Daniel Henrique Barboza
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-09-11hw/riscv: virt: Fix riscv,pmu DT node pathConor Dooley
2023-09-11target/riscv: select KVM AIA in riscv virt machineYong-Xuan Wang
2023-09-11target/riscv: update APLIC and IMSIC to support KVM AIAYong-Xuan Wang
2023-09-11target/riscv: Create an KVM AIA irqchipYong-Xuan Wang
2023-09-11target/riscv: check the in-kernel irqchip supportYong-Xuan Wang
2023-09-11target/riscv: support the AIA device emulation with KVM enabledYong-Xuan Wang
2023-09-11linux-user/riscv: Use abi type for target_ucontextLIU Zhiwei
2023-09-11hw/intc: Make rtc variable names consistentJason Chien
2023-09-11hw/intc: Fix upper/lower mtime write calculationJason Chien
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei
2023-09-11target/riscv: Add Zihintntl extension ISA string to DTSJason Chien
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou
2023-09-11crypto: Add SM4 constant parameter CKMax Chou
2023-09-11crypto: Create sm4_subwordMax Chou
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood
2023-09-11target/riscv: Move vector translation checksNazar Kazakov
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk
2023-09-11target/riscv: Use existing lookup tables for MixColumnsArd Biesheuvel
2023-09-11target/riscv: Fix page_check_range use in fault-only-firstLIU Zhiwei
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza
2023-09-11hw/char/riscv_htif: Fix the console syscall on big endian hostsThomas Huth
2023-09-11hw/char/riscv_htif: Fix printing of console characters on big endian hostsThomas Huth
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza
2023-09-08arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZEShameer Kolothum
2023-09-08target/arm: Enable SCTLR_EL1.TIDCP for user-onlyRichard Henderson
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