Age | Commit message (Collapse) | Author |
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Gilboa.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3328 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3327 c046a42c-6fe2-441c-8c8c-71466251a162
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Kenigsberg.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3326 c046a42c-6fe2-441c-8c8c-71466251a162
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patch by Dan Kenigsberg.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3325 c046a42c-6fe2-441c-8c8c-71466251a162
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Don't abort on illegal GPSR reads, instead only warn.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3324 c046a42c-6fe2-441c-8c8c-71466251a162
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effect is implementation dependant.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3323 c046a42c-6fe2-441c-8c8c-71466251a162
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* fix the tunable cache line size probe for PowerPC 970.
* initialize HID5 so cache line is 32 bytes long when running in user-mode only
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3322 c046a42c-6fe2-441c-8c8c-71466251a162
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Implement dcbz tunable cache line size for PowerPC 970.
Make hardware reset vector implementation dependant.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3321 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3320 c046a42c-6fe2-441c-8c8c-71466251a162
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Cleanups in MMU exceptions generation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3319 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3318 c046a42c-6fe2-441c-8c8c-71466251a162
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reset must occur after we defined the CPU features.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3317 c046a42c-6fe2-441c-8c8c-71466251a162
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Protect PowerPC 64 only features with #ifdef (TARGET_PPC64)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3316 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3315 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3314 c046a42c-6fe2-441c-8c8c-71466251a162
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Add comments in load & store tables to ease code reading.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3313 c046a42c-6fe2-441c-8c8c-71466251a162
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on 32 bits hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3312 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3311 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3310 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3309 c046a42c-6fe2-441c-8c8c-71466251a162
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exceptions from op helpers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3308 c046a42c-6fe2-441c-8c8c-71466251a162
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of supporting code.
Implement 74xx software TLB model.
Keep 74xx with software TLB disabled, as Linux is not able to handle TLB miss
on those processors.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3307 c046a42c-6fe2-441c-8c8c-71466251a162
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Tag unused functions with unused attribute instead of using #ifdef (TODO)
to ease tests: just have to enable the implementation in the cpu_defs table.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3306 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3305 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3304 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3303 c046a42c-6fe2-441c-8c8c-71466251a162
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call the helpers directly from the micro-ops.
Avoid duplicated code for tlbsx. implementation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3302 c046a42c-6fe2-441c-8c8c-71466251a162
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Add comments about some unimplemented storage control dedicated SPRs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3301 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3300 c046a42c-6fe2-441c-8c8c-71466251a162
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Fix critical input interrupt generation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3299 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3298 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3297 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3296 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3295 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3294 c046a42c-6fe2-441c-8c8c-71466251a162
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(crash reported by Andreas Farber when using default CPU).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3293 c046a42c-6fe2-441c-8c8c-71466251a162
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(problem reported by Andreas Farber).
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3292 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3291 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3290 c046a42c-6fe2-441c-8c8c-71466251a162
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- New mtmsr/mtmsrd form that just update RI and EE bits
- New hrfid, lq and stq instructions
- Add support for supervisor and hypervisor modes process priority update
- Code provision for hypervisor SPR accesses
* Actually implement the wait instruction
* Bugfixes (missing RETURN in micro-op / missing #ifdef)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3289 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3288 c046a42c-6fe2-441c-8c8c-71466251a162
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* fix invalid instructions bits masks
* new wait instruction
* more comments about effect of cache instructions on the MMU
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3287 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3286 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3285 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
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This is a rework of Stefan Weil proposed patch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3283 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3282 c046a42c-6fe2-441c-8c8c-71466251a162
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as defined in the PowerPC 2.04 specification.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3281 c046a42c-6fe2-441c-8c8c-71466251a162
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as the PowerPC registers only store double-precision floats,
use float64_to_float32 & float32_to_float64 to do the appropriate conversion.
Implement stfiwx.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3280 c046a42c-6fe2-441c-8c8c-71466251a162
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according to the PowerPC 2.04 specification.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3279 c046a42c-6fe2-441c-8c8c-71466251a162
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