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2022-03-04tcg/i386: Implement avx512 multiplyRichard Henderson
AVX512DQ has VPMULLQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 min/max/absRichard Henderson
AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Expand scalar rotate with avx512 insnsRichard Henderson
Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V; expand 16-bit scalar rotate with VPSHLDV. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Remove rotls_vec from tcg_target_op_defRichard Henderson
There is no such instruction on x86, so we should not be pretending it has arguments. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Expand vector word rotate as avx512vbmi2 shift-doubleRichard Henderson
While there are no specific 16-bit rotate instructions, there are double-word shifts, which can perform the same operation. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Support avx512vbmi2 vector shift-double instructionsRichard Henderson
We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 variable rotateRichard Henderson
AVX512VL has VPROLVD and VPRORVQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 immediate rotateRichard Henderson
AVX512VL has VPROLD and VPROLQ, layered onto the same opcode as PSHIFTD, but requires EVEX encoding and W1. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 immediate sari shiftRichard Henderson
AVX512 has VPSRAQ with immediate operand, in the same form as with AVX, but requires EVEX encoding and W1. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 scalar shiftRichard Henderson
AVX512VL has VPSRAQ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Implement avx512 variable shiftsRichard Henderson
AVX512VL has VPSRAVQ, and AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinvRichard Henderson
The condition for UMIN/UMAX availability is about to change; use the canonical version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Add tcg_out_evex_opcRichard Henderson
The evex encoding is added here, for use in a subsequent patch. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/i386: Detect AVX512Richard Henderson
There are some operation sizes in some subsets of AVX512 that are missing from previous iterations of AVX. Detect them. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/s390x: Implement vector NAND, NOR, EQVRichard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/ppc: Implement vector NAND, NOR, EQVRichard Henderson
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Add opcodes for vector nand, nor, eqvRichard Henderson
We've had placeholders for these opcodes for a while, and should have support on ppc, s390x and avx512 hosts. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg: Set MAX_OPC_PARAM_IARGS to 7Ziqiao Kong
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and thus the MAX_OPC_PARAM_IARGS should be 7. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com> Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04tcg/optimize: only read val after const checkAlex Bennée
valgrind pointed out that arg_info()->val can be undefined which will be the case if the arguments are not constant. The ordering of the checks will have ensured we never relied on an undefined value but for the sake of completeness re-order the code to be clear. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-04Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into ↵Peter Maydell
staging hw/nvme updates - add enhanced protection information (64-bit guard) # gpg: Signature made Fri 04 Mar 2022 06:23:36 GMT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * remotes/nvme/tags/nvme-next-pull-request: hw/nvme: 64-bit pi support hw/nvme: add pi tuple size helper hw/nvme: add support for the lbafee hbs feature hw/nvme: move format parameter parsing hw/nvme: add host behavior support feature hw/nvme: move dif/pi prototypes into dif.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-04Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-nios-20220303' ↵Peter Maydell
into staging Rewrite nios2 interrupt handling # gpg: Signature made Thu 03 Mar 2022 19:52:33 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-nios-20220303: target/nios2: Rewrite interrupt handling target/nios2: Special case ipending in rdctl and wrctl target/nios2: Split mmu_write target/nios2: Hoist R_ZERO check in rdctl target/nios2: Only build mmu.c for system mode target/nios2: Replace MMU_LOG with tracepoints target/nios2: Remove mmu_read_debug Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging Fifth RISC-V PR for QEMU 7.0 * Fixup checks for ext_zb[abcs] * Add AIA support for virt machine * Increase maximum number of CPUs in virt machine * Fixup OpenTitan SPI address * Add support for zfinx, zdinx and zhinx{min} extensions # gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20220303: target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv: add support for zhinx/zhinxmin target/riscv: add support for zdinx target/riscv: add support for zfinx target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} hw: riscv: opentitan: fixup SPI addresses hw/riscv: virt: Increase maximum number of allowed CPUs docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Add optional AIA IMSIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine target/riscv: fix inverted checks for ext_zb[abcs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03target/nios2: Rewrite interrupt handlingRichard Henderson
Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts are disabled at a particular point in time, instead queuing the value into cpu->irq_pending. This is more complicated than required. Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt, and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Special case ipending in rdctl and wrctlRichard Henderson
It was never correct to be able to write to ipending. Until the rest of the irq code is tidied, the read of ipending will generate an "unnecessary" mask. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Split mmu_writeRichard Henderson
Create three separate functions for the three separate registers. Avoid extra dispatch through op_helper.c. Dispatch to the correct function in translation. Clean up the ifdefs in wrctl. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Hoist R_ZERO check in rdctlRichard Henderson
This will avoid having to replicate the check to additional cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Only build mmu.c for system modeRichard Henderson
We can thus remove an ifdef covering the entire file. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Replace MMU_LOG with tracepointsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03target/nios2: Remove mmu_read_debugRichard Henderson
This functionality can be had via plugins, if desired. In the meantime, it is unused code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-03-03Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20220302' into staging target-arm queue: * mps3-an547: Add missing user ahb interfaces * hw/arm/mps2-tz.c: Update AN547 documentation URL * hw/input/tsc210x: Don't abort on bad SPI word widths * hw/i2c: flatten pca954x mux device * target/arm: Support PSCI 1.1 and SMCCC 1.0 * target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv() * tests/qtest: add qtests for npcm7xx sdhci * Implement FEAT_LVA * Implement FEAT_LPA * Implement FEAT_LPA2 (but do not enable it yet) * Report KVM's actual PSCI version to guest in dtb * ui/cocoa.m: Fix updateUIInfo threading issues * ui/cocoa.m: Remove unnecessary NSAutoreleasePools # gpg: Signature made Wed 02 Mar 2022 20:52:06 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20220302: (26 commits) ui/cocoa.m: Remove unnecessary NSAutoreleasePools ui/cocoa.m: Fix updateUIInfo threading issues target/arm: Report KVM's actual PSCI version to guest in dtb target/arm: Implement FEAT_LPA2 target/arm: Advertise all page sizes for -cpu max target/arm: Validate tlbi TG matches translation granule in use target/arm: Fix TLBIRange.base for 16k and 64k pages target/arm: Introduce tlbi_aa64_get_range target/arm: Extend arm_fi_to_lfsc to level -1 target/arm: Implement FEAT_LPA target/arm: Implement FEAT_LVA target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA target/arm: Honor TCR_ELx.{I}PS target/arm: Use MAKE_64BIT_MASK to compute indexmask target/arm: Pass outputsize down to check_s2_mmu_setup target/arm: Move arm_pamax out of line target/arm: Fault on invalid TCR_ELx.TxSZ target/arm: Set TCR_EL1.TSZ for user-only hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N> tests/qtest: add qtests for npcm7xx sdhci ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03hw/nvme: 64-bit pi supportNaveen Nagar
This adds support for one possible new protection information format introduced in TP4068 (and integrated in NVMe 2.0): the 64-bit CRC guard and 48-bit reference tag. This version does not support storage tags. Like the CRC16 support already present, this uses a software implementation of CRC64 (so it is naturally pretty slow). But its good enough for verification purposes. This may go nicely hand-in-hand with the support that Keith submitted for the Linux kernel[1]. [1]: https://lore.kernel.org/linux-nvme/20220126165214.GA1782352@dhcp-10-100-145-180.wdc.com/T/ Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03hw/nvme: add pi tuple size helperKlaus Jensen
A subsequent patch will introduce a new tuple size; so add a helper and use that instead of sizeof() and magic numbers. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03hw/nvme: add support for the lbafee hbs featureNaveen Nagar
Add support for up to 64 LBA formats through the LBAFEE field of the Host Behavior Support feature. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03hw/nvme: move format parameter parsingKlaus Jensen
There is no need to extract the format command parameters for each namespace. Move it to the entry point. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03hw/nvme: add host behavior support featureNaveen Nagar
Add support for getting and setting the Host Behavior Support feature. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03hw/nvme: move dif/pi prototypes into dif.hKlaus Jensen
Move dif/pi data structures and inlines to dif.h. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li
- update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN - update half float point register read/write - disable nanbox_h check Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: add support for zdinxWeiwei Li
-- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: add support for zfinxWeiwei Li
- update extension check REQUIRE_ZFINX_OR_F - update single float point register read/write - disable nanbox_s check Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1 base addresses. Also adds these as unimplemented devices. The address references can be found [1]. [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel
To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-6-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03docs/system: riscv: Document AIA options for virt machineAnup Patel
We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-5-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel
We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts as MSIs to the AIA IMSIC. We also provide "aia-guests=<xyz>" parameter which can be used to specify number of VS-level AIA IMSIC Guests MMIO pages for each HART. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220220085526.808674-4-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03hw/intc: Add RISC-V AIA IMSIC device emulationAnup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt files. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-3-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel
We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220220085526.808674-2-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] inadvertently became inverted and slipped through the initial testing (which used RV64GC_XVentanaCondOps as a target). This fixes the regression. Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs. Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through DisasContext") Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-02Merge remote-tracking branch ↵Peter Maydell
'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging Migration/HMP/Virtio pull 2022-03-02 A bit of a mix this time: * Minor fixes from myself, Hanna, and Jack * VNC password rework by Stefan and Fabian * Postcopy changes from Peter X that are the start of a larger series to come * Removing the prehistoic load_state_old code from Peter M Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Wed 02 Mar 2022 18:25:12 GMT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert-gitlab/tags/pull-migration-20220302b: migration: Remove load_state_old and minimum_version_id_old tests: Pass in MigrateStart** into test_migrate_start() migration: Add migration_incoming_transport_cleanup() migration: postcopy_pause_fault_thread() never fails migration: Enlarge postcopy recovery to capture !-EIO too migration: Move static var in ram_block_from_stream() into global migration: Add postcopy_thread_create() migration: Dump ramblock and offset too when non-same-page detected migration: Introduce postcopy channels on dest node migration: Tracepoint change in postcopy-run bottom half migration: Finer grained tracepoints for POSTCOPY_LISTEN migration: Dump sub-cmd name in loadvm_process_command tp migration/rdma: set the REUSEADDR option for destination qapi/monitor: allow VNC display id in set/expire_password qapi/monitor: refactor set/expire_password with enums monitor/hmp: add support for flag argument with value virtiofsd: Let meson check for statx.stx_mnt_id clock-vmstate: Add missing END_OF_LIST Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-25 16:17:04 +0000