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2014-04-18tcg: Relax requirement for mulu2_i32 on 32-bit hostsRichard Henderson
Instead require either mulu2_i32 or muluh_i32. The code in tcg-op.h already supports looking for both. Previous incomplete conversion? Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-s390: Remove W constraintRichard Henderson
Now redundant with the type parameter to tcg_target_const_match. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-sparc: Use the type parameter to tcg_target_const_matchRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-ppc64: Use the type parameter to tcg_target_const_matchRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg-aarch64: Remove w constraintRichard Henderson
Now redundant with the type parameter to tcg_target_const_match. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson
Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix out of range shift in deposit optimizationsRichard Henderson
By inspection, for a deposit(x, y, 0, 64), we'd have a shift of (1<<64) and everything else falls apart. But we can reuse the existing deposit logic to get this right. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tci: Mask shift counts to avoid undefined behaviorRichard Henderson
TCG now requires unspecified behavior rather than a potential crash, bring the C shift within the letter of the law. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Mask shift quantities while foldingRichard Henderson
The TCG result would be undefined, but we can at least produce one plausible result and avoid triggering the wrath of analysis tools. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Use "unspecified behavior" for shiftsRichard Henderson
Change the definition such that shifts are not allowed to crash for any input. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix warning (1 bit signed bitfield entry) and replace int by boolStefan Weil
Static code analyzers complain about signed bitfields with only a single bit. is_ld is used as a boolean value, so make it bool. ppc64 already used bool for the 2nd argument is_ld of the local function add_qemu_ldst_label. Modify all other TCG targets to do follow this example. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-17Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20140417-1' into staging target-arm queue: * AArch64 system mode support; this is all the CPU emulation code but not the virt board support * cadence_ttc match register bugfix * Allwinner A10 PIC, PIT and ethernet fixes [with update to avoid duplicate typedef] * zynq-slcr rewrite * cadence_gem bugfix * fix for SMLALD/SMLSLD insn in A32 * fix for SQXTUN in A64 # gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits) target-arm: A64: fix unallocated test of scalar SQXTUN arm: translate.c: Fix smlald Instruction net: cadence_gem: Make phy respond to broadcast misc: zynq_slcr: Make DB_PRINTs always compile misc: zynq_slcr: Convert SBD::init to object init misc: zynq-slcr: Rewrite allwinner-emac: update irq status after writes to interrupt registers allwinner-emac: set autonegotiation complete bit on link up allwinner-a10-pit: implement prescaler and source selection allwinner-a10-pit: use level triggered interrupts allwinner-a10-pit: avoid generation of spurious interrupts allwinner-a10-pic: fix behaviour of pending register allwinner-a10-pic: set vector address when an interrupt is pending timer: cadence_ttc: Fix match register write logic target-arm/gdbstub64.c: remove useless 'break' statement. target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc target-arm: Make Cortex-A15 CBAR read-only target-arm: Implement CBAR for Cortex-A57 target-arm: Implement Cortex-A57 implementation-defined system registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm: A64: fix unallocated test of scalar SQXTUNAlex Bennée
The test for the U bit was incorrectly inverted in the scalar case of SQXTUN. This doesn't affect the vector case as the U bit is used to select XTN(2). Reported-by: Hao Liu <hao.liu@arm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17arm: translate.c: Fix smlald InstructionPeter Crosthwaite
The smlald (and probably smlsld) instruction was doing incorrect sign extensions of the operands amongst 64bit result calculation. The instruction psuedo-code is: operand2 = if m_swap then ROR(R[m],16) else R[m]; product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); result = product1 + product2 + SInt(R[dHi]:R[dLo]); R[dHi] = result<63:32>; R[dLo] = result<31:0>; The result calculation should be done in 64 bit arithmetic, and hence product1 and product2 should be sign extended to 64b before calculation. The current implementation was adding product1 and product2 together then sign-extending the intermediate result leading to false negatives. E.G. if product1 = product2 = 0x4000000, their sum = 0x80000000, which will be incorrectly interpreted as -ve on sign extension. We fix by doing the 64b extensions on both product1 and product2 before any addition/subtraction happens. We also fix where we were possibly incorrectly setting the Q saturation flag for SMLSLD, which the ARM ARM specifically says is not set. Reported-by: Christina Smith <christina.smith@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 2cddb6f5a15be4ab8d2160f3499d128ae93d304d.1397704570.git.peter.crosthwaite@xilinx.com Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17net: cadence_gem: Make phy respond to broadcastPeter Crosthwaite
Phys must respond to address 0 by specification. Implement. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 6f4d53b04ddbfb19895bfb61a595e69f1c08859a.1396594056.git.peter.crosthwaite@xilinx.com Reviewed-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17misc: zynq_slcr: Make DB_PRINTs always compilePeter Crosthwaite
Change the DB_PRINT macro over to a regular if() rather than conditional compilation to give constant compile testing of formats. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 942477847353c5cff5f45a228cc88c633dc012f3.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17misc: zynq_slcr: Convert SBD::init to object initPeter Crosthwaite
To bring it up to date with styling guidelines. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2e837af80a18216c21e73241032e048f39d78b99.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17misc: zynq-slcr: RewritePeter Crosthwaite
Near total rewrite of this device model. It is stylistically obsolete, has numerous coverity fails and is not up to date with latest Xilinx documentation. Fix. The registers are flattened into a single array. This greatly simplifies the MMIO accessor functions. We take the oppurtunity to update the register Macro definitions to match the latest TRM. Xilinx has de-documented some regs hence there are some straight deletions. We only do this however in the case or a stock read-as-written reset-zero register. Non-zero resets are always preserved. New register definitions are added as needed. This all comes with a VMSD version break as the union layout from before was a bit strange and we are better off without it. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3aa016167b352ed224666909217137285fd3351d.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-emac: update irq status after writes to interrupt registersBeniamino Galvani
The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-8-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-emac: set autonegotiation complete bit on link upBeniamino Galvani
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-7-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani
This implements the prescaler and source fields of the timer control register. The source for each timer can be selected among 4 clock inputs whose frequencies are set through model properties. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-6-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pit: use level triggered interruptsBeniamino Galvani
Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-5-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pit: avoid generation of spurious interruptsBeniamino Galvani
The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing explicitly the timer index to the callback function. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-4-git-send-email-b.galvani@gmail.com [PMM: avoid duplicate typedef of AwA10PITState] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pic: fix behaviour of pending registerBeniamino Galvani
The pending register is read-only and the value returned upon a read reflects the state of irq input pins (interrupts are level triggered). This patch implements such behaviour. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-3-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17allwinner-a10-pic: set vector address when an interrupt is pendingBeniamino Galvani
This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com> Message-id: 1395771730-16882-2-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17timer: cadence_ttc: Fix match register write logicPeter Crosthwaite
This switch logic should not fall through. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 74147b4c017c904364955cc73107f90e6ac8ba74.1396326389.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm/gdbstub64.c: remove useless 'break' statement.Chen Gang
Clean up useless 'break' statement after 'return' statement. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell
For system mode, we may have a 64 bit CPU which is currently executing in AArch32 state; if we're dumping CPU state to the logs we should therefore show the correct state for the current execution state, rather than hardwiring it based on the type of the CPU. For consistency with how we handle translation, we leave the 32 bit dump function as the default, and have it hand off control to the 64 bit dump code if we're in AArch64 mode. Reported-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-17target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pcPeter Maydell
The AArch64 implementation of the set_pc method needs to be updated to handle the possibility that the CPU is in AArch32 mode; otherwise there are weird crashes when doing interprocessing in system emulation mode when an interrupt occurs and we fail to resynchronize the 32-bit PC with the TB we need to execute next. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Make Cortex-A15 CBAR read-onlyPeter Maydell
The Cortex-A15's CBAR register is actually read-only (unlike that of the Cortex-A9). Correct our model to match the hardware. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell
The Cortex-A57, like most of the other ARM cores, has a CBAR register which defines the base address of the per-CPU peripherals. However it has a 64-bit view as well as a 32-bit view; expand the QOM reset-cbar property from UINT32 to UINT64 so this can be specified, and implement the 32-bit and 64-bit views of a 64-bit CBAR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement Cortex-A57 implementation-defined system registersPeter Maydell
Implement a subset of the Cortex-A57's implementation defined system registers. We provide RAZ/WI or reads-as-constant/writes-ignored implementations of the various control and syndrome reigsters. We do not implement registers which provide direct access to and manipulation of the L1 cache, since QEMU doesn't implement caches. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement RVBAR registerPeter Maydell
Implement the AArch64 RVBAR register, which indicates the reset address. Since the reset address is implementation defined and usually configurable by setting config signals in hardware, we also provide a QOM property so it can be set at board level if necessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 address translation operationsPeter Maydell
Implement the AArch64 address translation operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement auxiliary fault status registersPeter Maydell
Implement the auxiliary fault status registers AFSR0_EL1 and AFSR1_EL1. These are present on v7 and later, and have IMPDEF behaviour; we choose to RAZ/WI for all cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8Peter Maydell
Many of the reginfo definitions in cp_reginfo[] use CP_ANY wildcards. This is for a combination of reasons: * early ARM implementations really did underdecode * earlier versions of QEMU underdecoded and we can't tighten this up because we don't know if guests really require this or not * implementation convenience For ARMv8 the architecture has tightened things up and system and coprocessor registers are always specifically decoded. We take advantage of this opportunity for a clean break by restricting our CP_ANY wildcarded reginfo to pre-v8 CPUs, and providing specifically decoded versions where necessary for v8 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Don't expose wildcard ID register definitions for ARMv8Peter Maydell
In ARMv8 the 32 bit coprocessor ID register space is tidied up to remove the wildcarded aliases of the MIDR and the RAZ behaviour for the unassigned space where crm = 3..7. Make sure we don't expose thes wildcards for v8 cores. This means we need to have a specific implementation for REVIDR, an IMPDEF register which may be the same as the MIDR (and which we always implement as such). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Remove THUMB2EE feature from AArch64 'any' CPUPeter Maydell
The AArch64 usermode 'any' CPU type was accidentally specified with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since ARMv8 removes Thumb2EE completely. Since we never implemented Thumb2EE anyway having the feature bit set was fairly harmless for user-mode, but the correct thing is to not set it at all. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement ISR_EL1 registerPeter Maydell
Implement the ISR_EL1 register. This is actually present in ARMv7 as well but was previously unimplemented. It is a read-only register that indicates whether interrupts are currently pending. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 view of ACTLRPeter Maydell
Implement the AArch64 view of the ACTLR (auxiliary control register). Note that QEMU internally tends to call this AUXCR for historical reasons. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 view of CONTEXTIDRPeter Maydell
Implement AArch64 view of the CONTEXTIDR register. We tighten up the condition when we flush the TLB on a CONTEXTIDR write to avoid needlessly flushing the TLB every time on a 64 bit system (and also on a 32 bit system using LPAE, as a bonus). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 views of AArch32 ID registersPeter Maydell
All the AArch32 ID registers are visible from AArch64 (in addition to the AArch64-specific ID_AA64* registers). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Add Cortex-A57 processorPeter Maydell
Add Cortex-A57 processor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell
For ARMv8 there are two changes to the MVFR media feature registers: * there is a new MVFR2 which is accessible from 32 bit code * 64 bit code accesses these via the usual sysreg instructions rather than with a floating-point specific instruction Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or AArch32 EL0 are supported. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: fixed minor style nits; updated to match changes in previous patches; added some of the simpler cases of illegal-exception-return support] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Move arm_log_exception() into internals.hPeter Maydell
Move arm_log_exception() into internals.h so we can use it from helper-a64.c for the AArch64 exception entry code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 SPSR_EL1Peter Maydell
Implement the AArch64 SPSR_EL1. For compatibility with how KVM handles SPSRs and with the architectural mapping between AArch32 and AArch64, we put this in the banked_spsr[] array in the slot that is used for SVC in AArch32. This means we need to extend the array from uint32_t to uint64_t, which requires some reworking of the 32 bit KVM save/restore code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement SP_EL0, SP_EL1Peter Maydell
Implement handling for the AArch64 SP_EL0 system register. This holds the EL0 stack pointer, and is only accessible when it's not being used as the stack pointer, ie when we're in EL1 and EL1 is using its own stack pointer. We also provide a definition of the SP_EL1 register; this isn't guest visible as a system register for an implementation like QEMU which doesn't provide EL2 or EL3; however it is useful for ensuring the underlying state is migrated. We need to update the state fields in the CPU state whenever we switch stack pointers; this happens when we take an exception and also when SPSEL is used to change the bit in PSTATE which indicates which stack pointer EL1 should use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Add AArch64 ELR_EL1 register.Peter Maydell
Add the AArch64 ELR_EL1 register. Note that this does not live in env->cp15: for KVM migration compatibility we need to migrate it separately rather than as part of the system registers, because the KVM-to-userspace interface puts it in the struct kvm_regs rather than making them visible via the ONE_REG ioctls. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-17target-arm: Implement AArch64 views of fault status and data registersRob Herring
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit DFSR, DFAR, IFAR share state with them as architecturally specified. The IFSR doesn't share state with any AArch64 register visible at EL1, so just rename the state field without widening it to 64 bits. Signed-off-by: Rob Herring <rob.herring@linaro.org> [PMM: Minor tweaks; fix some bugs involving inconsistencies between use of offsetof() or offsetoflow32() and struct field width] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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