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-rw-r--r--tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c64
-rw-r--r--tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c4
-rw-r--r--tests/tcg/mips/mips32-dsp/mulq_rs_ph.c19
-rw-r--r--tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c24
4 files changed, 96 insertions, 15 deletions
diff --git a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c
index ce864844d9..cbf900713f 100644
--- a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c
+++ b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c
@@ -14,7 +14,7 @@ int main()
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
- "mtlo %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
@@ -27,8 +27,8 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
- ach = 0x12;
- acl = 0x48;
+ ach = 0x00000012;
+ acl = 0x00000048;
rs = 0x80000000;
rt = 0x80000000;
@@ -37,7 +37,7 @@ int main()
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
- "mtlo %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
@@ -51,16 +51,64 @@ int main()
assert(acl == resultl);
ach = 0x741532A0;
- acl = 0xfceabb08;
+ acl = 0xFCEABB08;
rs = 0x80000000;
rt = 0x80000000;
- resulth = 0x7fffffff;
- resultl = 0xffffffff;
+ resulth = 0x7FFFFFFF;
+ resultl = 0xFFFFFFFF;
resultdsp = 0x01;
__asm
("mthi %0, $ac1\n\t"
- "mtlo %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "dpaq_sa.l.w $ac1, %3, %4\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ "rddsp %2\n\t"
+ : "+r"(ach), "+r"(acl), "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ dsp = (dsp >> 17) & 0x01;
+ assert(dsp == resultdsp);
+ assert(ach == resulth);
+ assert(acl == resultl);
+
+ ach = 0;
+ acl = 0;
+ rs = 0xC0000000;
+ rt = 0x7FFFFFFF;
+
+ resulth = 0xC0000000;
+ resultl = 0x80000000;
+ resultdsp = 0;
+ __asm
+ ("wrdsp $0\n\t"
+ "mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "dpaq_sa.l.w $ac1, %3, %4\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ "rddsp %2\n\t"
+ : "+r"(ach), "+r"(acl), "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ dsp = (dsp >> 17) & 0x01;
+ assert(dsp == resultdsp);
+ assert(ach == resulth);
+ assert(acl == resultl);
+
+ ach = 0x20000000;
+ acl = 0;
+ rs = 0xE0000000;
+ rt = 0x7FFFFFFF;
+
+ resulth = 0;
+ resultl = 0x40000000;
+ resultdsp = 0;
+ __asm
+ ("wrdsp $0\n\t"
+ "mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
"dpaq_sa.l.w $ac1, %3, %4\n\t"
"mfhi %0, $ac1\n\t"
"mflo %1, $ac1\n\t"
diff --git a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c
index b7b73fdb66..eda3b14e2b 100644
--- a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c
+++ b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c
@@ -9,8 +9,8 @@ int main()
rs = 0xBC0123AD;
rt = 0x01643721;
- resulth = 0xfdf4cbe0;
- resultl = 0xd138776b;
+ resulth = 0x00BD3A22;
+ resultl = 0xD138776B;
resultdsp = 0x00;
__asm
("mthi %0, $ac1\n\t"
diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c
index c7206039ea..370c2a8018 100644
--- a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c
+++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c
@@ -12,7 +12,24 @@ int main()
resultdsp = 1;
__asm
- ("mulq_rs.ph %0, %2, %3\n\t"
+ ("wrdsp $0\n\t"
+ "mulq_rs.ph %0, %2, %3\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rd), "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ dsp = (dsp >> 21) & 0x01;
+ assert(rd == result);
+ assert(dsp == resultdsp);
+
+ rs = 0x80011234;
+ rt = 0x80024321;
+ result = 0x7FFD098C;
+ resultdsp = 0;
+
+ __asm
+ ("wrdsp $0\n\t"
+ "mulq_rs.ph %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)
diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
index 3535b37a58..da6845bf24 100644
--- a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
+++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c
@@ -12,18 +12,34 @@ int main()
result = 0x12348765;
__asm
- ("precrq_rs.ph.w %0, %1, %2\n\t"
+ ("wrdsp $0\n\t"
+ "precrq_rs.ph.w %0, %1, %2\n\t"
: "=r"(rd)
: "r"(rs), "r"(rt)
);
assert(result == rd);
- rs = 0x7fffC678;
+ rs = 0x7FFFC678;
rt = 0x865432A0;
- result = 0x7fff8654;
+ result = 0x7FFF8654;
__asm
- ("precrq_rs.ph.w %0, %2, %3\n\t"
+ ("wrdsp $0\n\t"
+ "precrq_rs.ph.w %0, %2, %3\n\t"
+ "rddsp %1\n\t"
+ : "=r"(rd), "=r"(dsp)
+ : "r"(rs), "r"(rt)
+ );
+ assert(((dsp >> 22) & 0x01) == 1);
+ assert(result == rd);
+
+ rs = 0xBEEFFEED;
+ rt = 0x7FFF8000;
+ result = 0xBEF07FFF;
+
+ __asm
+ ("wrdsp $0\n\t"
+ "precrq_rs.ph.w %0, %2, %3\n\t"
"rddsp %1\n\t"
: "=r"(rd), "=r"(dsp)
: "r"(rs), "r"(rt)