diff options
Diffstat (limited to 'tests/data/acpi/virt')
26 files changed, 8005 insertions, 0 deletions
diff --git a/tests/data/acpi/virt/APIC.dsl b/tests/data/acpi/virt/APIC.dsl new file mode 100644 index 0000000000..d334cef533 --- /dev/null +++ b/tests/data/acpi/virt/APIC.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.memhp.dsl b/tests/data/acpi/virt/APIC.memhp.dsl new file mode 100644 index 0000000000..9b86f7b984 --- /dev/null +++ b/tests/data/acpi/virt/APIC.memhp.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.numamem.dsl b/tests/data/acpi/virt/APIC.numamem.dsl new file mode 100644 index 0000000000..2d43338766 --- /dev/null +++ b/tests/data/acpi/virt/APIC.numamem.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/DSDT.dsl b/tests/data/acpi/virt/DSDT.dsl new file mode 100644 index 0000000000..58368ff44c --- /dev/null +++ b/tests/data/acpi/virt/DSDT.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001450 (5200) + * Revision 0x02 + * Checksum 0xFA + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, Zero) // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.memhp.dsl b/tests/data/acpi/virt/DSDT.memhp.dsl new file mode 100644 index 0000000000..84f3c51867 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.memhp.dsl @@ -0,0 +1,2215 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000019A6 (6566) + * Revision 0x02 + * Checksum 0x02 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & One) == One)) + { + \_SB.MHPC.MSCN () + } + + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + + If (((Local0 & 0x04) == 0x04)) + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + } + + Device (\_SB.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09070000, // Address Base + 0x00000018, // Address Length + ) + }) + OperationRegion (HPMR, SystemMemory, 0x09070000, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y00, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.numamem.dsl b/tests/data/acpi/virt/DSDT.numamem.dsl new file mode 100644 index 0000000000..6603d31a01 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.numamem.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001455 (5205) + * Revision 0x02 + * Checksum 0xE1 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/FACP.dsl b/tests/data/acpi/virt/FACP.dsl new file mode 100644 index 0000000000..2c73796f89 --- /dev/null +++ b/tests/data/acpi/virt/FACP.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.memhp.dsl b/tests/data/acpi/virt/FACP.memhp.dsl new file mode 100644 index 0000000000..0083b95ef7 --- /dev/null +++ b/tests/data/acpi/virt/FACP.memhp.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.numamem.dsl b/tests/data/acpi/virt/FACP.numamem.dsl new file mode 100644 index 0000000000..aee15bd4c2 --- /dev/null +++ b/tests/data/acpi/virt/FACP.numamem.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/GTDT.dsl b/tests/data/acpi/virt/GTDT.dsl new file mode 100644 index 0000000000..1ab06dd3c2 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.memhp.dsl b/tests/data/acpi/virt/GTDT.memhp.dsl new file mode 100644 index 0000000000..d78bb092c5 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.memhp.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.numamem.dsl b/tests/data/acpi/virt/GTDT.numamem.dsl new file mode 100644 index 0000000000..5c3c2a83db --- /dev/null +++ b/tests/data/acpi/virt/GTDT.numamem.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/MCFG.dsl b/tests/data/acpi/virt/MCFG.dsl new file mode 100644 index 0000000000..f09c86f487 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.memhp.dsl b/tests/data/acpi/virt/MCFG.memhp.dsl new file mode 100644 index 0000000000..b03a6384e8 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.memhp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.numamem.dsl b/tests/data/acpi/virt/MCFG.numamem.dsl new file mode 100644 index 0000000000..303df803f5 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.numamem.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/NFIT.dsl b/tests/data/acpi/virt/NFIT.dsl new file mode 100644 index 0000000000..947ba0f6a4 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/NFIT.memhp.dsl b/tests/data/acpi/virt/NFIT.memhp.dsl new file mode 100644 index 0000000000..84511bff96 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.memhp.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SLIT.dsl b/tests/data/acpi/virt/SLIT.dsl new file mode 100644 index 0000000000..34276fca96 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SLIT.memhp.dsl b/tests/data/acpi/virt/SLIT.memhp.dsl new file mode 100644 index 0000000000..a17f948af2 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SPCR.dsl b/tests/data/acpi/virt/SPCR.dsl new file mode 100644 index 0000000000..3c271412cf --- /dev/null +++ b/tests/data/acpi/virt/SPCR.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.memhp.dsl b/tests/data/acpi/virt/SPCR.memhp.dsl new file mode 100644 index 0000000000..81e00457cc --- /dev/null +++ b/tests/data/acpi/virt/SPCR.memhp.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.numamem.dsl b/tests/data/acpi/virt/SPCR.numamem.dsl new file mode 100644 index 0000000000..faf6729797 --- /dev/null +++ b/tests/data/acpi/virt/SPCR.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SRAT.dsl b/tests/data/acpi/virt/SRAT.dsl new file mode 100644 index 0000000000..f267aabc67 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SRAT.memhp.dsl b/tests/data/acpi/virt/SRAT.memhp.dsl new file mode 100644 index 0000000000..3f311e6be0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.memhp.dsl @@ -0,0 +1,107 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E2 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 5C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +[06Ah 0106 1] Subtable Type : 01 [Memory Affinity] +[06Bh 0107 1] Length : 28 + +[06Ch 0108 4] Proximity Domain : 00000001 +[070h 0112 2] Reserved1 : 0000 +[072h 0114 8] Base Address : 0000000048000000 +[07Ah 0122 8] Address Length : 0000000008000000 +[082h 0130 4] Reserved2 : 00000000 +[086h 0134 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[08Ah 0138 8] Reserved3 : 0000000000000000 + +[092h 0146 1] Subtable Type : 01 [Memory Affinity] +[093h 0147 1] Length : 28 + +[094h 0148 4] Proximity Domain : 00000001 +[098h 0152 2] Reserved1 : 0000 +[09Ah 0154 8] Base Address : 0000000088000000 +[0A2h 0162 8] Address Length : 0000000008000000 +[0AAh 0170 4] Reserved2 : 00000000 +[0AEh 0174 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[0B2h 0178 8] Reserved3 : 0000000000000000 + +[0BAh 0186 1] Subtable Type : 01 [Memory Affinity] +[0BBh 0187 1] Length : 28 + +[0BCh 0188 4] Proximity Domain : 00000001 +[0C0h 0192 2] Reserved1 : 0000 +[0C2h 0194 8] Base Address : 0000000080000000 +[0CAh 0202 8] Address Length : 00000000F0000000 +[0D2h 0210 4] Reserved2 : 00000000 +[0D6h 0214 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[0DAh 0218 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 226 (0xE2) + + 0000: 53 52 41 54 E2 00 00 00 03 5C 42 4F 43 48 53 20 // SRAT.....\BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 0070: 00 00 00 00 00 48 00 00 00 00 00 00 00 08 00 00 // .....H.......... + 0080: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 01 28 01 00 00 00 00 00 00 00 00 88 00 00 // ...(............ + 00A0: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 05 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 00C0: 00 00 00 00 00 80 00 00 00 00 00 00 00 F0 00 00 // ................ + 00D0: 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 // .. diff --git a/tests/data/acpi/virt/SRAT.numamem.dsl b/tests/data/acpi/virt/SRAT.numamem.dsl new file mode 100644 index 0000000000..b6e59b1af0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SSDT.dsl b/tests/data/acpi/virt/SSDT.dsl new file mode 100644 index 0000000000..cb220787b4 --- /dev/null +++ b/tests/data/acpi/virt/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/SSDT.memhp, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002E0 (736) + * Revision 0x01 + * Checksum 0x3F + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemMemory, 0x09090000, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x43D10000) +} + |