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-rw-r--r--tcg/tcg-op.h12
-rw-r--r--tcg/tcg-opc.h5
-rw-r--r--tcg/tcg.c29
3 files changed, 43 insertions, 3 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index b354100e65..b92b7bd162 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1291,6 +1291,18 @@ static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
#error must include QEMU headers
#endif
+/* debug info: write the PC of the corresponding QEMU CPU instruction */
+static inline void tcg_gen_debug_insn_start(uint64_t pc)
+{
+ /* XXX: must really use a 32 bit size for TCGArg in all cases */
+#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
+ tcg_gen_op2i(INDEX_op_debug_insn_start,
+ (uint32_t)(pc), (uint32_t)(pc >> 32));
+#else
+ tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
+#endif
+}
+
static inline void tcg_gen_exit_tb(tcg_target_long val)
{
tcg_gen_op1i(INDEX_op_exit_tb, val);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index a80056a22d..ca5bd0b81d 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -156,6 +156,11 @@ DEF2(neg_i64, 1, 1, 0, 0)
#endif
/* QEMU specific */
+#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
+DEF2(debug_insn_start, 0, 0, 2, 0)
+#else
+DEF2(debug_insn_start, 0, 0, 1, 0)
+#endif
DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4e3094b7ca..1c1bb9fabe 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -743,17 +743,31 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
const uint16_t *opc_ptr;
const TCGArg *args;
TCGArg arg;
- int c, i, k, nb_oargs, nb_iargs, nb_cargs;
+ int c, i, k, nb_oargs, nb_iargs, nb_cargs, first_insn;
const TCGOpDef *def;
char buf[128];
+ first_insn = 1;
opc_ptr = gen_opc_buf;
args = gen_opparam_buf;
while (opc_ptr < gen_opc_ptr) {
c = *opc_ptr++;
def = &tcg_op_defs[c];
- fprintf(outfile, " %s ", def->name);
- if (c == INDEX_op_call) {
+ if (c == INDEX_op_debug_insn_start) {
+ uint64_t pc;
+#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
+ pc = ((uint64_t)args[1] << 32) | args[0];
+#else
+ pc = args[0];
+#endif
+ if (!first_insn)
+ fprintf(outfile, "\n");
+ fprintf(outfile, " ---- 0x%" PRIx64, pc);
+ first_insn = 0;
+ nb_oargs = def->nb_oargs;
+ nb_iargs = def->nb_iargs;
+ nb_cargs = def->nb_cargs;
+ } else if (c == INDEX_op_call) {
TCGArg arg;
/* variable number of arguments */
@@ -762,6 +776,8 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
nb_iargs = arg & 0xffff;
nb_cargs = def->nb_cargs;
+ fprintf(outfile, " %s ", def->name);
+
/* function name */
fprintf(outfile, "%s",
tcg_get_helper_str_idx(s, buf, sizeof(buf), args[nb_oargs + nb_iargs - 1]));
@@ -785,6 +801,7 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
}
}
} else {
+ fprintf(outfile, " %s ", def->name);
if (c == INDEX_op_nopn) {
/* variable number of arguments */
nb_cargs = *args;
@@ -1037,6 +1054,9 @@ void tcg_liveness_analysis(TCGContext *s)
/* mark end of basic block */
tcg_la_bb_end(s, dead_temps);
break;
+ case INDEX_op_debug_insn_start:
+ args -= def->nb_args;
+ break;
case INDEX_op_nopn:
nb_args = args[-1];
args -= nb_args;
@@ -1840,6 +1860,9 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
dead_iargs = s->op_dead_iargs[op_index];
tcg_reg_alloc_mov(s, def, args, dead_iargs);
break;
+ case INDEX_op_debug_insn_start:
+ /* debug instruction */
+ break;
case INDEX_op_nop:
case INDEX_op_nop1:
case INDEX_op_nop2: