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path: root/tcg/x86_64/tcg-target.c
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Diffstat (limited to 'tcg/x86_64/tcg-target.c')
-rw-r--r--tcg/x86_64/tcg-target.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index 33327d1d11..60968327b3 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -194,6 +194,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define ARITH_XOR 6
#define ARITH_CMP 7
+#define SHIFT_ROL 0
+#define SHIFT_ROR 1
#define SHIFT_SHL 4
#define SHIFT_SHR 5
#define SHIFT_SAR 7
@@ -1049,7 +1051,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
case INDEX_op_sar_i32:
c = SHIFT_SAR;
goto gen_shift32;
-
+ case INDEX_op_rotl_i32:
+ c = SHIFT_ROL;
+ goto gen_shift32;
+ case INDEX_op_rotr_i32:
+ c = SHIFT_ROR;
+ goto gen_shift32;
+
case INDEX_op_shl_i64:
c = SHIFT_SHL;
gen_shift64:
@@ -1070,7 +1078,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
case INDEX_op_sar_i64:
c = SHIFT_SAR;
goto gen_shift64;
-
+ case INDEX_op_rotl_i64:
+ c = SHIFT_ROL;
+ goto gen_shift64;
+ case INDEX_op_rotr_i64:
+ c = SHIFT_ROR;
+ goto gen_shift64;
+
case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
args[3], 0);
@@ -1230,6 +1244,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_shl_i32, { "r", "0", "ci" } },
{ INDEX_op_shr_i32, { "r", "0", "ci" } },
{ INDEX_op_sar_i32, { "r", "0", "ci" } },
+ { INDEX_op_rotl_i32, { "r", "0", "ci" } },
+ { INDEX_op_rotr_i32, { "r", "0", "ci" } },
{ INDEX_op_brcond_i32, { "r", "ri" } },
@@ -1259,6 +1275,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
{ INDEX_op_shl_i64, { "r", "0", "ci" } },
{ INDEX_op_shr_i64, { "r", "0", "ci" } },
{ INDEX_op_sar_i64, { "r", "0", "ci" } },
+ { INDEX_op_rotl_i64, { "r", "0", "ci" } },
+ { INDEX_op_rotr_i64, { "r", "0", "ci" } },
{ INDEX_op_brcond_i64, { "r", "re" } },