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-rw-r--r--tcg/i386/tcg-target.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 73a15f7e80..2fd28fa6a5 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -108,6 +108,7 @@ extern bool have_popcnt;
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_goto_ptr 1
+#define TCG_TARGET_HAS_direct_jump 1
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extrl_i64_i32 0
@@ -166,6 +167,14 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
}
+static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
+ uintptr_t jmp_addr, uintptr_t addr)
+{
+ /* patch the branch destination */
+ atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
+ /* no need to flush icache explicitly */
+}
+
/* This defines the natural memory order supported by this
* architecture before guarantees made by various barrier
* instructions.