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-rw-r--r--target/xtensa/cpu.h1
-rw-r--r--target/xtensa/overlay_tool.h8
-rw-r--r--target/xtensa/translate.c60
3 files changed, 46 insertions, 23 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 7a46dccbe1..32749378bf 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -464,6 +464,7 @@ struct XtensaConfig {
XtensaMemory sysrom;
XtensaMemory sysram;
+ unsigned hw_version;
uint32_t configid[2];
void *isa_internal;
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index cab532095c..a994e69b6e 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -60,8 +60,9 @@
#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
#endif
-#ifndef XCHAL_HW_MIN_VERSION
-#define XCHAL_HW_MIN_VERSION 0
+#ifndef XCHAL_HW_VERSION
+#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \
+ + XCHAL_HW_VERSION_MINOR)
#endif
#ifndef XCHAL_LOOP_BUFFER_SIZE
@@ -100,7 +101,7 @@
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
- XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
+ XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
/* Interrupts and exceptions */ \
@@ -498,6 +499,7 @@
}
#define CONFIG_SECTION \
+ .hw_version = XCHAL_HW_VERSION, \
.configid = { \
XCHAL_HW_CONFIGID0, \
XCHAL_HW_CONFIGID1, \
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index e0beaf7abb..6346b2eef0 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -595,9 +595,6 @@ static int gen_postprocess(DisasContext *dc, int slot)
gen_io_start();
}
gen_helper_check_interrupts(cpu_env);
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- }
}
#endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
@@ -2191,7 +2188,11 @@ static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ if (sr_name[par[0]]) {
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2363,9 +2364,10 @@ static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
#ifdef CONFIG_USER_ONLY
bool ill = true;
#else
- bool ill = !semihosting_enabled();
+ /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
+ bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
#endif
- if (ill) {
+ if (ill || !semihosting_enabled()) {
qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
}
return ill;
@@ -2375,7 +2377,9 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- gen_helper_simcall(cpu_env);
+ if (semihosting_enabled()) {
+ gen_helper_simcall(cpu_env);
+ }
#endif
}
@@ -2563,13 +2567,17 @@ static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+ if (sr_name[par[0]]) {
+ tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
+ }
}
static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
+ if (sr_name[par[0]]) {
+ tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
+ }
}
static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
@@ -2775,23 +2783,31 @@ static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_temp_new_i32();
+ if (sr_name[par[0]]) {
+ TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp, arg[0].in);
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
- tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
- tcg_temp_free(tmp);
+ tcg_gen_mov_i32(tmp, arg[0].in);
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
+ tcg_temp_free(tmp);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
- TCGv_i32 tmp = tcg_temp_new_i32();
+ if (sr_name[par[0]]) {
+ TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_mov_i32(tmp, arg[0].in);
- tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
- tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
- tcg_temp_free(tmp);
+ tcg_gen_mov_i32(tmp, arg[0].in);
+ tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
+ tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
+ tcg_temp_free(tmp);
+ } else {
+ tcg_gen_movi_i32(arg[0].out, 0);
+ }
}
static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2819,7 +2835,11 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
{ \
TCGv_i32 tmp = tcg_temp_new_i32(); \
\
- tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
+ if (sr_name[par[0]]) { \
+ tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
+ } else { \
+ tcg_gen_movi_i32(tmp, 0); \
+ } \
translate_wsr_##name(dc, arg, par); \
tcg_gen_mov_i32(arg[0].out, tmp); \
tcg_temp_free(tmp); \
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-03 07:04:04 +0000