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Diffstat (limited to 'target')
-rw-r--r--target/i386/monitor.c6
-rw-r--r--target/loongarch/tlb_helper.c2
-rw-r--r--target/microblaze/op_helper.c2
-rw-r--r--target/mips/tcg/sysemu/tlb_helper.c2
-rw-r--r--target/ppc/mmu-hash32.c14
-rw-r--r--target/ppc/mmu-hash64.c12
-rw-r--r--target/ppc/mmu_common.c26
-rw-r--r--target/ppc/mmu_helper.c4
-rw-r--r--target/riscv/cpu_helper.c10
-rw-r--r--target/riscv/monitor.c2
-rw-r--r--target/sparc/ldst_helper.c6
-rw-r--r--target/sparc/mmu_helper.c10
-rw-r--r--target/tricore/helper.c2
13 files changed, 49 insertions, 49 deletions
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 8e4b4d600c..ad5b7b8bb5 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -57,7 +57,7 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
{
addr = addr_canonical(env, addr);
- monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
+ monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx
" %c%c%c%c%c%c%c%c%c\n",
addr,
pte & mask,
@@ -258,8 +258,8 @@ static void mem_print(Monitor *mon, CPUArchState *env,
prot1 = *plast_prot;
if (prot != prot1) {
if (*pstart != -1) {
- monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
- TARGET_FMT_plx " %c%c%c\n",
+ monitor_printf(mon, HWADDR_FMT_plx "-" HWADDR_FMT_plx " "
+ HWADDR_FMT_plx " %c%c%c\n",
addr_canonical(env, *pstart),
addr_canonical(env, end),
addr_canonical(env, end - *pstart),
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index c6d1de50fe..cce1db1e0a 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -655,7 +655,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
return true;
} else {
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 5b745d0928..f6378030b7 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -403,7 +403,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
CPUMBState *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
- " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n",
+ " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
addr, physaddr, size,
access_type == MMU_INST_FETCH ? "INST_FETCH" :
(access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 9d16859c0a..e5e1e9dd3f 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -924,7 +924,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
switch (ret) {
case TLBRET_MATCH:
qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
break;
default:
diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index cc091c3e62..3976416840 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -346,24 +346,24 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
ptem = (vsid << 7) | (pgidx >> 10);
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " ptem=%" PRIx32
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
vsid, ptem, hash);
pteg_off = get_pteg_offset32(cpu, hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
- qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=%" PRIx32 " api=%" PRIx32
- " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
pteg_off = get_pteg_offset32(cpu, ~hash);
pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index b9b31fd276..900f906990 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -697,15 +697,15 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
/* Page address translation */
qemu_log_mask(CPU_LOG_MMU,
- "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
/* Primary PTEG lookup */
qemu_log_mask(CPU_LOG_MMU,
- "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n",
+ " hash=" HWADDR_FMT_plx "\n",
ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
vsid, ptem, hash);
ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
@@ -714,9 +714,9 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
/* Secondary PTEG lookup */
ptem |= HPTE64_V_SECONDARY;
qemu_log_mask(CPU_LOG_MMU,
- "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
+ "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
- " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
+ " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 8901f4d134..7235a4befe 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -252,7 +252,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
}
if (best != -1) {
done:
- qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx
" prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
@@ -328,7 +328,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
ctx->prot = prot;
ret = check_prot(ctx->prot, access_type);
if (ret == 0) {
- qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_FMT_plx
" prot=%c%c\n", i, ctx->raddr,
ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
@@ -403,9 +403,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
/* Check if instruction fetch is allowed, if needed */
if (type != ACCESS_CODE || ctx->nx == 0) {
/* Page address translation */
- qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
- " htab_mask " TARGET_FMT_plx
- " hash " TARGET_FMT_plx "\n",
+ qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
+ " htab_mask " HWADDR_FMT_plx
+ " hash " HWADDR_FMT_plx "\n",
ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
ctx->hash[0] = hash;
ctx->hash[1] = ~hash;
@@ -420,7 +420,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
- qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
+ qemu_log("Page table: " HWADDR_FMT_plx " len " HWADDR_FMT_plx
"\n", ppc_hash32_hpt_base(cpu),
ppc_hash32_hpt_mask(cpu) + 0x80);
for (curaddr = ppc_hash32_hpt_base(cpu);
@@ -432,7 +432,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
a2 = ldl_phys(cs->as, curaddr + 8);
a3 = ldl_phys(cs->as, curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
- qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
+ qemu_log(HWADDR_FMT_plx ": %08x %08x %08x %08x\n",
curaddr, a0, a1, a2, a3);
}
}
@@ -578,14 +578,14 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
return 0;
}
}
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx
+ " => " HWADDR_FMT_plx
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
@@ -666,11 +666,11 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__,
address, raddr, ctx->prot, ret);
}
@@ -894,11 +894,11 @@ found_tlb:
if (ret >= 0) {
ctx->raddr = raddr;
qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
ctx->raddr, ctx->prot, ret);
} else {
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
- " => " TARGET_FMT_plx " %d %d\n", __func__, address,
+ " => " HWADDR_FMT_plx " %d %d\n", __func__, address,
raddr, ctx->prot, ret);
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 2a91f3f46a..64e30435f5 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -826,7 +826,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
tlb->prot &= ~PAGE_VALID;
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx " size " TARGET_FMT_lx
" prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
@@ -864,7 +864,7 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
if (val & PPC4XX_TLBLO_WR) {
tlb->prot |= PAGE_WRITE;
}
- qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx
+ qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx
" EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8ea3442b4a..9a28816521 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1272,7 +1272,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s 1st-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
@@ -1285,7 +1285,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, im_address, ret, pa, prot2);
prot &= prot2;
@@ -1295,7 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
@@ -1320,7 +1320,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, address, ret, pa, prot);
if (ret == TRANSLATE_SUCCESS) {
@@ -1328,7 +1328,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
size, access_type, mode);
qemu_log_mask(CPU_LOG_MMU,
- "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ "%s PMP address=" HWADDR_FMT_plx " ret %d prot"
" %d tlb_size " TARGET_FMT_lu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 17e63fab00..236f93b9f5 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -64,7 +64,7 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
return;
}
- monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
+ monitor_printf(mon, TARGET_FMT_lx " " HWADDR_FMT_plx " " TARGET_FMT_lx
" %c%c%c%c%c%c%c\n",
addr_canonical(va_bits, vaddr),
paddr, size,
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index ec4fae78c3..a53580d9e4 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -430,12 +430,12 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
#ifdef DEBUG_UNASSIGNED
if (is_asi) {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" asi 0x%02x from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, is_asi, env->pc);
} else {
- printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
+ printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx
" from " TARGET_FMT_lx "\n",
is_exec ? "exec" : is_write ? "write" : "read", size,
size == 1 ? "" : "s", addr, env->pc);
@@ -490,7 +490,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr,
CPUSPARCState *env = &cpu->env;
#ifdef DEBUG_UNASSIGNED
- printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
+ printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx
"\n", addr, env->pc);
#endif
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 919448a494..158ec2ae8f 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -230,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
if (likely(error_code == 0)) {
qemu_log_mask(CPU_LOG_MMU,
"Translate at %" VADDR_PRIx " -> "
- TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
address, paddr, vaddr);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return true;
@@ -356,27 +356,27 @@ void dump_mmu(CPUSPARCState *env)
hwaddr pa;
uint32_t pde;
- qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
+ qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n",
(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va);
- qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
+ qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx
" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
pde = mmu_probe(env, va1, 1);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va1);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
+ HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n",
va1, pa, pde);
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
pde = mmu_probe(env, va2, 0);
if (pde) {
pa = cpu_get_phys_page_debug(cs, va2);
qemu_printf(" VA: " TARGET_FMT_lx ", PA: "
- TARGET_FMT_plx " PTE: "
+ HWADDR_FMT_plx " PTE: "
TARGET_FMT_lx "\n",
va2, pa, pde);
}
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 1db32808e8..114685cce4 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -79,7 +79,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
address, rw, mmu_idx);
qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
- TARGET_FMT_plx " prot %d\n",
+ HWADDR_FMT_plx " prot %d\n",
__func__, (target_ulong)address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-29 00:27:12 +0000